Abstract
ABSTRACTGlobal Planarization requirements of the deep sub-micron technology generation requires use of CMP as preferred planarization technique. In the past, CMP has been used extensively in the polishing of silicon wafers. However , there has been some reluctance to utilize this technology in the planarization of oxide films during IC manufacture. This has been driven primarily by issues regarding manufacturability , and therefore cost of ownership of CMP processes. Here the key process integration issues in CMP planarization of oxide films are outlined.An effect of consumable set is shown to be critical in achieving repeatable CMP performance via removal rate & non-uniformity. Various defects induced as a result of CMP are explained. Cost of ownership model is used to demonstrate the importance of minimizing such defects.
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