Abstract
In this article, we characterized the charge trapping and detrapping behaviors of charge-trap transistors (CTTs) in standard 28-nm CMOS technology and formulated its programmable threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ). Both thin-oxide and thick-oxide CTT devices are measured, modeled, and analyzed. More than 50- and 100-mV continuous V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> tuning ranges are achieved for thin and thick oxide devices, respectively. Multiple cycles of programming and erasing operations are demonstrated; however, the reliability needs to be solved in the future. To utilize the developed programmable threshold model, a nonvolatile memory (NVM) cell and an analog arithmetic unit (AAU) are proposed and simulated as two proof-of-concept CTT-based designs.
Highlights
The emerging nonvolatile device has aroused increasing attention due to its advantages in building the on-chip nonvolatile memory (NVM) cell and computing-in-memory (CIM) element [1]
Compared with other charge-trapping devices, such as floating-gate transistors [3], transistors with an organic gate dielectric [4], and carbon nanotube transistors [5], charge-trap transistors (CTTs) are fully logic-CMOS-compatible in terms of process, operating voltage, and manufacturing maturity, which has been proven in 22-nm planar SOI and 14-nm FinFET technology without adding any process complexity or masks [6]
MEASUREMENT SETUP AND PROGRAMMING CONDITIONS A test chip is fabricated in 28-nm CMOS technology to characterize the charge trapping and detrapping behavior and the programmable VTH
Summary
The emerging nonvolatile device has aroused increasing attention due to its advantages in building the on-chip nonvolatile memory (NVM) cell and computing-in-memory (CIM) element [1]. A CTT device is a standard NMOS device We measured the threshold voltage tuning behavior due to charge trapping and detrapping in standard 28-nm CMOS technology. 1) Characterize CTT programmable threshold voltage (VTH) and trapping and detrapping behavior for the first time using standard 28-nm bulk CMOS technology. 4) Propose two proof-of-concept circuit-level designs: an NVM cell and an analog arithmetic unit (AAU).
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