Abstract

THE availability of the Silicon on Insulator (SOI) process at OKI Inc. (now Lapis Semiconductor) with an handle wafer of moderate resistivity and contacts through the buried oxide layer has promoted a significant R&D on monolithic Si pixel sensors for charged particle tracking and imaging. The SOI technology has a number of potential advantages compared to bulk CMOS processes for the fabrication of pixel sensors. Past the first proof of principle of beam particle detection with an SOI pixel sensor [1], the R&D had to solve the back-gating effect, which limited the practical depletion voltage and thus the depleted thickness. The use of a buried p-well to protect the CMOS electronics from the potential on the handle wafer has successfully solved this problem and SOI pixels developed by KEK and by our group (LBNL, UCSC and INFN, Padova) have demonstrated full functionality up to 90 V and above [2], [3], [4]. This corresponds to a depleted thicknesses of ≃130 µm for a nominal resistivity of 700 O·cm.

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