Chapter 4 - Instruction Sets

Abstract

This chapter provides an insight into the instruction set in the Cortex-M3 and examples for a number of instructions. The Cortex-M3 provides many different instructions for data processing. Many data operation instructions can have multiple instruction formats. For instance, an ADD instruction can operate between two registers or between one register and an immediate data value. Aside from ADD instructions, the arithmetic functions that the Cortex-M3 supports include SUB (subtract), MUL (multiply), and UDIV/SDIV (unsigned and signed divide). The Cortex-M3 also supports 32-bit multiply instructions and multiply accumulate instructions that give 64-bit results. These instructions support signed or unsigned values. Additionally, the Cortex-M3 provides rotate and shift instructions. In some cases, the rotate operation can be combined with other operations such as in memory address offset calculation for load/store instructions. Furthermore, the Cortex-M3 supports a number of barrier instructions. These instructions are needed as memory systems get more and more complex. In some cases, if memory barrier instructions are not used, race conditions could occur. For instance, if a hardware register can switch the memory map, after writing to the memory switching register you should use the DSB instruction. Otherwise, if the write to the memory switching register is buffered and takes a few cycles to complete, and the next instruction accesses the switched memory region immediately, the access could be using the old memory map.