Chapter 17 - Interrupt Latency

Abstract

Latency is defined as the longest time between when the interrupt occurs and when the central processing unit (CPU) suspends the current processing context. Latency as defined by CPU vendors varies from zero to the max time specified. Many CPUs include looping constructs that can take hundreds, even thousands of microseconds. A block memory-to-memory transfer, for instance, initiated by a single instruction, might run for an awfully long time, driving latency figures out of sight. The block move will be suspended, but enough context is saved to allow the transfer to resume when the interrupt service routine (ISR) completes. So, the latency figure in the datasheet reveals the longest time the processor can't service interrupts. The second biggest cause of latency is excessive use of the disable interrupts instruction. Shared resources—global variables, hardware, and the like—will cause erratic crashes when two asynchronous activities try to access them simultaneously. It's up to designers to keep the code reentrant by either keeping all such accesses atomic, or by limiting access to a single task at a time. The classic approach is to disable interrupts around such accesses.