Abstract
The CDF data acquisition and trigger system is being upgraded to significantly increase the bandwidth for the upcoming high luminosity running of the Tevatron Collider (run IIb). This paper focuses on the upgrade for the level 2 (L2) trigger decision crate. This crate is at the heart of the L2 trigger system and has to interface with many different subsystems both upstream and downstream. The challenge of this upgrade is to have a uniform design to be able to interface with many different data paths upstream, merge and process the data at high speed for fast L2 trigger decision making, and minimize the impact on the running CDF experiment during the commissioning phase. In order to meet this challenge, the design philosophy of the upgrade is to use one type of general purpose motherboard, with a few powerful modern FPGAs and SRAMs, to interface any user data with any industrial standard link through the use of mezzanine cards. This general purpose motherboard, named (PULSer And Recorder), is fully self-testable at board level as well as at system level. CERN S-LINK is chosen to allow Pulsar to communicate with commodity processors via high bandwidth, low latency S-LINK-to-PCI cards. Knowledge gained by using S-LINK at CDF will be transferable to and from the LHC community.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
