Cause-Effect Chains Analysis Using Boolean Algebra

Although current methods for digital and analog circuit testing in the NAVY Automatic Test Equipment (ATE) environment are adequate, there are limitations and pitfalls. These can be due to inadequate transfer of information between the design and test of a circuit card resulting in untestable circuits. This can lead to expensive and time consuming test generation. Next Generation Test Generator (NGTG) has developed a process that will generate tests and diagnostic data using genetic algorithms and neural networks. This paper describes the procedure that will be used to interface NGTG and the ATE. NGTG will be demonstrated on Consolidated Automated Support System (CASS). For digital circuit testing, the CASS environment uses the Digital Test Unit (DTU). This environment requires diagnostic data in a unique language, L200, to process information. The NGTG system must interface with the DTU via Abbreviated Test Language for All Systems (ATLAS) code. ATLAS uses a Functional External Program (FEP) to interface with the DTU. This paper will describe the two options and the necessary steps to demonstrate NGTG on CASS. These options involve diagnostic data in the proposed IEEE-P1445 Standard, Digital Test Interchange Format (DTIF) formatted files and new NGTG/FEP interfaces.

This special issue of the VLSI DESIGN: an International Journal of Custom-Chip Design, Simulation and Testing is devoted to spectral techniques, new types of decision trees and diagrams, their applications, efficient ways of their calculation and mutual relations between spectral techniques and classical decision diagrams. Manipulations and calculations with discrete functions are fundamental tasks in many areas of Computer Science and Engineering. Many problems in digital system design, simulation and testing can be expressed as a sequence of operations on discrete functions. The performance of Computer-Aided Design systems used in solving various problems in this area strongly depends on the efficiency of representations of discrete functions. Decision Diagrams (DDs) have proved very convenient data structure for discrete function representations, permitting manipulations and calculations with large functions efficiently in terms of time and space. In many applications, as for example those involving large matrices, conventional algorithms are significantly improved by using DDs. In logic design, such applications relate to basic problems of the design, verification, simulation and testing logical networks. Besides Boolean functions, some other types of discrete representations, such as multi-valued functions, cube sets, EXOR-based spectral and probabilistic formulas have to be dealt with. Hence the numbers of different decision trees and diagrams have been introduced for these various applications and representations. The spectral or polynomial representation of Boolean function is obtained by expressing it in terms of an orthogonal basis. The most popular basis is formed by discrete Walsh functions. Note that the spectral and the polynomial representation of a Boolean function are equivalent. The discrete orthogonal functions are referred to as the basis functions when the spectral or abstract harmonic terminology is used and as monomials when the polynomial terminology is used. Such polynomial representations have extensive applications in coding theory and cryptography as well as design of nonlinear filters. Spectral techniques based on Walsh, Haar, Arithmetic and Reed–Muller transforms have been used in digital logic design for more than 30 years. These techniques have been used for Boolean function classification, disjoint decomposition, identification of symmetries, parallel and serial linear decomposition, spectral translation synthesis (extraction of linear preand post-filters), multiplexer synthesis, threshold logic synthesis, state assignment and testing, and evaluation of logic complexity. The renewed interest in applications of spectral methods in design of VLSI digital circuits is caused by their excellent design for testability properties and in their efficiency in Boolean mapping problems. Furthermore, the practical applicability of these techniques was greatly improved with the development of efficient methods that allow calculating and operating on spectra of Boolean functions directly from reduced representations of such functions in the form of arrays of cubes or decision diagrams. Following from these recent developments, techniques have been presented for efficient spectral translation to decompose a circuit into a cascade of two sub circuits: linear block composed of EXOR gates fed by the primary input of the overall circuit. Such linear decomposition drastically simplifies the synthesis task. The choice of suitable linear transformation is based on a complexity measure assigned to each Boolean function that is heuristically related to the complexity of the final circuit implementation. To avoid the experimental costs of computing the Walsh transform, Binary Decision Diagrams (BDDs) based techniques are used. Recently the idea of linear transformations is applied to decision diagrams. By combining powerful spectral linear techniques with variable reordering techniques, it is possible to synthesize large Boolean functions with standard Computer-Aided Design tools that fail otherwise. The areas addressed by this special issue span spectral transforms, their applications and efficient calculation methods through decision diagrams. New spectral decision diagrams are also emerging that support larger data structures allowing more complex discrete representations to be implemented that was previously impossible.

Compaction methods have been successively used for off-line testing of both digital and analog circuits as well as on-line (concurrent) testing of digital circuits. In this work, we extend the use of compaction methods for concurrent testing of analog-to-digital converters. We estimate tolerance bounds for the result of compaction and evaluate the aliasing rate.

Derivative operations of the Boolean differential calculus are very useful for many applications, like the test of digital circuits, the synthesis using the bi-decomposition of Boolean functions, the specification of Boolean functions with regard to certain properties, etc. Basically, a derivative operation can be executed for a single Boolean function. Here we extend the known theory such that each of the ten derivative operations can be applied to classes \(\mathcal {C}_N\) of Boolean functions without the need to compute the derivative operation for each Boolean function of the class separately.

A conception of practical works for teaching design and test of digital circuits is presented. The works cover essential topics in testing and diagnostics field. They are meant for improving the skills of students to be educated for hardware and SoC design in test related topics. Six practical works are described. The works are based on two diagnostic software packages that were developed at Tallinn Technical University and Kharkov National Technical University of Radio Electronics. A brief description of these packages is given. All the training materials can be accessed over the Internet and therefore can be used by students at any time and any place. The free-access basis and self-contained nature makes it much easier to implement this course in foreign universities with a minimum of help from our side.

Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Conversion between those representations is common, especially when one is used to represent the input and another speeds up relevant algorithms. In the last 15 years, a number of applications based on efficient manipulation of Boolean functions gained industrial significance, notably in automated design and verification of logic circuits. The efficient representation and manipulation of Boolean functions is important for many algorithms in a wide variety of applications in particular, many problems in computer-aided design for digital circuits (CAD). The efficiency of the Boolean manipulation depends on the form of representation of the Boolean function. It is unavoidable and important problem to find a variable ordering which minimize the size of a BDD, since variable ordering has a great influence on the computation time and storage requirements for Boolean function manipulation number of times each variable takes part in the Logic operation to obtain the best possible the variable order. This paper describes a technique for finding the best variable ordering by analyzing the logic gate representation in the given Boolean function. Algorithm starts with initial variable ordering. The system will check each sub expression to find out the number times each variable takes part in each type of logic operations. The number of occurrences for each variable will be stored and then all the totals are arranged in descending order to identify the variable ordering for that Boolean function. If more than one input variables have the same total then a special criteria will be used to break the tie: We present graph-based evidence of the improvement obtained by using highly effective logical verification based variable ordering technique for BDDs. It is shown that the effectiveness of the Decision Diagram is mainly depending on the variable ordering selected. It is not practical to have any unique ordering for a given Boolean function and it can be selected among the number of best results, what will be more appropriate with the design. This new technique, easy to implement and automate, consistently creates high quality variable ordering for Boolean function.

The design methods presented in earlier chapters will allow an initial specification to be translated into a practical circuit whose logical behaviour is correct and whose operating speed and other physical factors are predictable and well defined. However, it is also necessary that such circuits operate reliably, and that any faults which affect their operation may be detected easily (and hence cheaply). In most cases, our systems are constructed from components (from simple gates to VLSI devices) which are assembled on to printed circuit boards. In such cases, a wide range of different faults can exist, from faulty components to incorrect PCB manufacture and assembly, and we require methods to detect and locate such faults. Obviously, if all components were perfect and no errors ever occurred during system manufacture, testing would be unnecessary, but, if the probability of correct component operation is C, then the probability, P n , of correct operation of a system containing n such components can be no better than C n , assuming that the failure of any component signifies failure of the system (since P n = C 1 × C 2 × ... × C n ). This means for example, that if C = 99% and the system contains 100 components, then P n = 37%, so that almost two-thirds of the systems produced may contain faults.

The stuck-at fault model is widely used as the basis for automatic test pattern generation in digital circuit testing, for example the D-algorithm. However, there have been growing doubts over the ability of the model to cover faults that occur in MOS LSI circuits. The paper consists of a review of the failure mechanisms that produce faults in MOS LSI circuits, a discussion of the problems that arise when using the stuck-at fault model to test MOS LSI circuits and a set of guidelines for the future development of computer-aided design and test of such circuits.

Context. Nonlinear systems of Boolean functions play a prominent role in the protection of cryptosystems. The creation and use of new four-bit cryptographic transformations with nonlinear Boolean functions that have the property of strict avalanche criterion is an actual task for increasing the reliability of information protection systems. Objective. The goal of the work is creating a method for obtaining inverse four-bit cryptographic transformations with the strict avalanche criterion property, which contain balanced Boolean functions only with the operations of inversion and addition modulo two. Method. A method is proposed for obtaining inverse four-bit cryptographic transformations with the strict avalanche criterion property, each of which contains balanced Boolean functions only with the operations of inversion and addition modulo two. The method simplifies the process of finding inverse cryptographic transformations by creating a class of thirty balanced basic Boolean functions with the required predefined limitations and properties and for finding, within this class, the basic Boolean functions that make up the inverse cryptographic transformation. Results. The effectiveness of the method is shown for obtaining two inverse four-bit cryptographic transformations with the property of a strict avalanche criterion from two direct four-bit cryptographic transformations with the property of a strict avalanche criterion. Conclusions. For the first time, there was proposed a method for obtaining inverse four-bit cryptographic transformations with the strict avalanche criterion property for balanced Boolean functions containing two logical operations (inversion and addition modulo two) to ensure reliable information protection. This method is a method of selecting the already existing basic Boolean functions from a predetermined set of balanced basic Boolean functions for direct and inverse cryptographic transformations, whereas the existing methods of searching for inverse cryptographic transformation are methods for calculating each element of the Boolean functions for the inverse cryptographic transformation. The method can be extended to a larger even number of arguments of the balanced Boolean functions of cryptographic transformations to increase the cryptographic resilience.

This paper introduces a novel architecture that is targeted for digital circuit testing application by means of Built-In Self-Test techniques. These applications consist of static configurable hardware designs that will execute the testing of the digital circuit in hardware, were previous literature has established It?s testing in software. Consequently introducing a hardware accelerator. In this paper we show the novel architecture to digital circuit testing in hardware on a reconfigurable processing unit for compile-time reconfiguration.

The digital integrated circuit (IC) testing model module is applied in this study to simulate the fabrication and testing of integrated circuits. The yield and quality of ICs are analyzed by assuming that the wafer devices under test conditions are normal probability distributions. The difficulties of testing and verification become increasingly great as the design function of the chip becomes remarkably complex. Conversely, the automotive industry chip supply chain has been substantially affected since the COVID-19 outbreak. The shortage of chips in the auto-market has always existed; therefore, increasing available chips under a limited production capacity has become a top priority. Therefore, this study applies the digital integrated circuit testing model (DITM) and proposes a retest plan. This method does not require considerable time to collect large wafer data, nor does it require additional hardware equipment. Furthermore, the required test quality parameters are set, and the test is repeated on the device by adjusting the test guardband (TGB). Moreover, three retesting schemes are proposed to improve the IC test quality (Yq) and test yield (Yt) to meet the requirements of consumers for product quality. A set of 2021 IEEE International Roadmap for Devices and Systems (IRDS) parameters is used to demonstrate the three proposed retesting schemes. The simulation results from the 2021 IRDS data prove that the retest method can effectively improve the test yield (Yt). A comparison of the estimated results of the three retest methods shows that using the repeat test method can maximize the test yield without sacrificing the test quality (Yq). By contrast, repeat testing can indeed improve the test yield (Yt) by 14% or more. Moreover, the increase in sellable ICs not only increases additional earnings for corporations, but also alleviates the current global shortage of automotive ICs.

In this paper, a method for maximum fault coverage with minimum power dissipation, during the testing of analog and digital circuits of mixed-signal System-on-Chip (SOC) simultaneously using Genetic Algorithm, (GA) is proposed. Mixed-signal SOC consists mainly of an analog block, a digital block and a DAC/ADC (Digital to Analog Converter/Analog to Digital Converter). Due to the presence of analog and digital circuits in mixed-signal SOCs, the testing procedure is difficult from that of only analog or digital circuit testing. Here stuck at 0/1 faults are considered for digital circuits, and stuck open/short faults are considered for analog circuits. In analog testing fault modeling, fault injection and fault simulation are done. The outputs of the analog block and some independent digital signals are given to the digital block. The GA-based approach is used for power-aware ordering of test patterns considering pattern dependency on previous patterns at the input of digital block as input patterns. The effect of noise on analog test signals has also been investigated here with the area analysis of the circuit. An average of 92.43% fault coverage and 13.56% maximum power saving is achieved when this methodology is applied to ITC 97 (Analog block) and ISCAS 85 (Digital block) benchmark circuits, respectively. A trade-off between fault coverage and power dissipation has been presented.

Map differentiation of switching functions

Testing of circuits became difficult as the scale of integration is increasing as said in Moore’s Law. Conventional testing approach is not sufficient with the growth of device counts and density. Testing helps the developer to investigate faults and error present in developed circuit which helps to reduce time require to test and thus decreases chances of getting failed during operation. Test time is one of the most important parameters in digital circuit testing which effects the overall process of testing. Reducing the test time of the test pattern generation is one of the most effected solution for the process. Reseeding LFSR is one of the methods to generate the test patterns for testing. In this paper, pseudo-random test patterns are generated to test circuit using reseeding LFSR technique. This helps to reduce the test pattern required to be stored for testing. This technique can be applied with the principles which are required for low power as well as low test data volume. Fault coverage of proposed circuit is calculated using ISCAS’89 benchmark circuits. The technique is integrated with the benchmark circuits and comparison is done based on the performance and resource utilization. Proposed model reduces the need for memory to store seed value and the power utilization. Reseeding can mainly be applied for BIST which targets complete fault coverage and minimization of the test length. Data compression for reducing the test pattern required for testing will indirectly reduce the time required to check the circuits. Future work is to reduce time required for the test pattern generation. Hamming distance can be applied to calculate the number of bits changing during the test patterns transition. Hamming distance approach can be implemented to reduce the parameter.

Automatic test pattern generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to recent advances in SAT- based proof engines. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not well suited Automatic Test Pattern Generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to recent advances in SAT- based proof engines. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not well suited for test compaction and compression. In this paper we present techniques to increase the number of unspecified bits in test patterns generated by SAT-based ATPG tools. We make use of structural properties of the circuit and apply local don't cares. Experimental results on industrial designs show significant reductions of up to 97% for test compaction and compression. In this paper we present techniques to increase the number of unspecified bits in test patterns generated by SAT-based ATPG tools. We make use of structural properties of the circuit and apply local don't cares. Experimental results on industrial designs show significant reductions of up to 97%.