Catastrophic faults in reconfigurable systolic linear arrays

Abstract

In regular architectures of identical processing elements, a widely used technique to improve the reconfigurability of the system consists of providing redundant processing elements and connections together with mechanisms of reconfiguration. In this paper we consider linear arrays of processing elements, with unidirectional bypass links of length g. We study those sets of faulty processing elements, called catastrophic, which prevent the reconfiguration. We show that the number of catastrophic faults of g elements is equal to the ( g − 1)th Catalan number. We also provide algorithms to rank and unrank all catastrophic sets of g faults. Finally, we describe a linear-time algorithm that generates all such sets of faults. Our results are useful to provide reliability estimates of linear arrays and for testing the behavior of reconfiguration strategies in the presence of catastrophic faults.