Cascaded Time Difference Amplifier with Differential Logic Delay Cell

Abstract

We introduce a 16x cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 μm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with ±150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.