Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy

Abstract

High capacity last-level caches (LLCs) are being used to help alleviate the growing speed gap between the processor and main memory. However, traditional CMOS based memory technologies (SRAM, DRAM, et al.) for such LLCs consume high static power. Non-volatile memory such as STT-MRAM has been proposed as a low power solution for LLCs. Nevertheless, the high write current induces a so-called “supply current threshold” issue and limits the maximum number of bit-cells that can be written concurrently in one cycle in an STT-MRAM cache. This drawback significantly decreases the bandwidth of the STT-MRAM cache compared with SRAM. In this work, we present a hardware implementation of NAND-like spintronic memory (NAND-SPIN) LLC for the first time. By exploiting the unique erase-then-program operation for writing NAND-SPIN, we propose an adaptive buffer entry (ABE) write policy for each cache write access. Instead of writing a fixed number of bits sequentially, our method adaptively extends the write data length under a fixed maximum cache supply current. Compared to existing STT-MRAM caches, ‘ABE’ can achieve 70% performance improvements on average. Compared with the conventional early write terminate (EWT) policy, ‘ABE’ can save 33% write energy on average with negligible hardware overhead.