Built-in Self-Calibration of On-chip DAC and ADC

Abstract

Linearity measurements are significant for assessing the performance of a modern mixed-signal system-on-chip. In this paper a new built-in self-test (BIST) scheme is presented for testing and calibration of on-chip high-resolution digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) for better linearity using sigma-delta modulator and low-resolution dithering DAC. Ramp signals are used as testing stimuli and responses of DAC-under-test (DUT) are measured by a first-order 1-bit sigma-delta modulator with high oversampling rate (OSR) and a low-pass digital filter for noise cancellation. A polynomial fit algorithm is used to characterize DAC and to obtain calibrating coefficients that determine whether the DUT passes or fails the test. DUT output error is compensated for by a dithering DAC with dynamic element matching (DEM) technique, which is controlled by the calibrating coefficients, to reduce the integral non-linearity (INL) error. Simulation results show that a sigma-delta modulator with effective number of bits (ENOB) equivalent to 17-bit ADC and a 6-bit low-cost dithering DAC are sufficient to calibrate a 14-bit high-resolution on-chip DAC such that the maximum INL error is reduced from 3 LSB to approximate 0.25 LSB. Testing and calibration of on-chip ADC using the same scheme is also discussed.