Breaking the Scalability Barrier of Content Addressable Memories: A Probabilistic Alternative for Large-Key Associative Search

Content addressable memory (CAM) is used as a hardware in lookup intensive applications. Despite high-speed feature, power consumption is the major limitation in CAM design. In this work, a compact CAM cell employing a high-speed comparison and evaluation is presented for a segmented NOR match-line (ML) with reduced ML capacitance. The non-pipeline CAM architecture minimizes switching activity of precharge and search at the cost of negligible overhead of a ML precharge and decision block. A 64×32-bit proposed macro is realized using 45-nm CMOS technology. Post-layout simulations at 1.1 V shows that proposed architecture achieves 203.60 ps search time while dissipating only 1.07 fJ/bit/search. Consequently, it leads to 71.24% and 84.85% energy-delay-product reductions over a conventional CAM and local-NOR global-NAND CAM, respectively. The proposed CAM based on two-segment configuration delivers ML power reductions of 12.26%-62.27% over the two CAMs. The proposed design is capable of operating efficiently at relatively low supply voltage and worst process corner.

Due to its capability of parallel search, content addressable memory (CAM) has been widely used on the applications requiring high-speed data search. In recent years, the architectures and design techniques for CAM have been consistently evolving. However, the incoming testing issues for those newly evolved CAM designs are not fully discussed. In this paper, we investigate the testing issues for a new 28nm quaternary CAM, which provides the additional fourth state compared to a conventional ternary CAM and utilizes a charge-sharing sensing scheme for reducing its search power consumption. We first identify the new fault models for this quaternary CAM that are not covered in the conventional CAM testing based on the simulation result, and derive the corresponding test algorithm for those new fault models. The effectiveness of the proposed test algorithm is then validated by the testing result of 7200 28nm sample chips covering different process corners with the help of a newly designed command-based memory BIST.

In this paper, Master Slave Match Line (MSML) design is adopted in conventional Content addressable memory (CAM) cell. The main objective of this design is to achieve Low power and high speed. MSML consists of two Master Match Line (MML) and two Slave Match Line (SML). The Circuit was implemented using Microwind tool in 45nm technology. Performance metrics such as power is compared with existing CAM designs like conventional CAM, NAND type CAM cell, NOR type CAM cell. Average Power consumption of the proposed design is found to be 36.944μW at 45nm for 1V. Delay in the signal propagation is measured as 0.011ns for 45nm technology. Proposed design achieves less power and high searching process than the conventional CAM cell.

This paper proposes a specialized memory structure called CA-RAM (content addressable random access memory) to accelerate search operations present in many important real-world applications. Search operations can occupy a significant portion of total execution time and energy consumption, while posing a difficult performance problem to tackle using traditional memory hierarchy concepts. In essence, CA-RAM is a direct hardware implementation of the well-known hashing technique. Searchable records are stored in CA-RAM at a location determined by a hash function, defined on their search key. After a database has been built, looking up a record in CA-RAM typically involves a single memory access followed by a parallel key matching operation. Compared with a conventional CAM (content addressable memory) solution, CA-RAM capitalizes on dense SRAM and DRAM designs, and achieves comparable search performance while occupying much smaller area and consuming significantly less power. This paper presents detailed design aspects of CA-RAM, to be integrated in future general-purpose and application-specific processors and systems. To further motivate and justify our approach, we present two real examples of using CA-RAM to build a high-performance search accelerator targeting: IP address lookup in core routers and trigram lookup in a large speech recognition system

We propose using caching to save power in content-addressable memories (CAMs). By using a small cache along with the CAM, we avoid accessing the larger and higher power CAM. For a cache hit rate of 90%, the cache-CAM (C-CAM) saves 80% power over a conventional CAM, for a cost of 15% increase in silicon area. Even at a low hit rate of 50%, a power savings of 40% is achieved. The proposed C-CAM is employed in the design of a testchip demonstrating a 2.6 fJ/bit/search in a 0.18 mum CMOS process

Low-power high-performance content-addressable memories (CAMs) are important components in modern computing systems. In this work, we present a robust CAM that overcomes the power and performance limitations of conventional precharge-based CAMs. The proposed static transmission gate-based (STAT-TG) CAM design achieves low-power operation comparable to NAND CAMs while maintaining search speeds rivaling those of NOR CAMs. The STAT-TG CAM was designed using a 65 nm CMOS technology and comprehensively evaluated under extensive Monte Carlo simulations. Compared to conventional CAMs, the STAT-TG CAM is 14% faster than NAND CAM, while consuming only 25% of the energy per operation relative to NOR CAM. This makes STAT-TG CAM a promising solution for high-performance yet energy-efficient applications.

Content addressable memory (CAM) is a fast lookup hardware table. However, its parallel comparison feature and frequent lookup cause significant power consumption. In this paper we propose a low power match-line architecture, called double match-line (DML) design, in which we combine the charge sharing and segmentation technique to largely reduce the CAM power dissipated in the ML switching activity. Unlike the conventional CAM design, where only a single ML is used, our design uses two MLs to perform the search operation. By reducing the ML swing, our design can minimize the charge loss in the search operation. Based on TSMC 90nm technology, the simulation results show that our design can reduce the search energy consumption of the CAM by 84% at most compared to the conventional NOR-type CAM design.

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other nonvolatile memories (NVMs). Content addressable memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging NVMs (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET-based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domains simultaneously. By exploiting the multilevel-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit codesign of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS-based CAM approaches, FeCAM is found to improve both memory density by 22.4× and energy saving by 8.6×/3.2× for analog/digital modes, respectively.In the CAM-related application, our evaluations show that FeCAM can achieve 60.5×/23.1× saving in area/search energy compared with conventional CMOS-based CAMs.

Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine

Low-power content addressable memory design using two-layer P-N match-line control and sensing

This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. The 128 × 144 bit CAM chip was fabricated using a 0.18 μm CMOS process with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.8 V. The CAM chip dissipates 2.82 fj/bit/search and consumes 8.7% of the power used by a conventional dynamic NOR-type CAM. It saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively. Its area is 1.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Its maximum operating frequency is 210 MHz.

In this paper, a novel Content Addressable Memory (CAM) word structure with divided word matching line for low-power application is proposed. To reduce the comparison power consumption, the proposed CAM word structure adopts static circuit design to improve the overall system reliability and reduce the power consumption. In addition, a new CAM cell with single bit line circuit design is proposed. The single bit line design requires only one heavy loading bit line, and prevents the frequently switching that designed in conventional basic CAM cell. Based on TSMC 0.25 /spl mu/m CMOS process with 2.5 V supply voltage, a 128 words by 32 bits CAM is designed. The simulation result shows that the power consumption of the proposed CAM is 17.12 mW under 300 MHz operation frequency.

Today, Content Addressable Memory (CAM) is used in a variety of applications, especially such as network routers. Because network routers need high speed, CAM is using NOR type rather than NAND type. However, due to frequent discharge of match line (ML), the power consumption of NOR type CAM is considerable. In this paper, we propose a low power NOR CAM using folded ML and charge recycling. The folded ML structure can reduce the ML voltage swing, and charge recycling can save pre-charge power, so the power consumption of the proposed CAM can be reduced. This proposed CAM has about 75.3% power consumption saving effect compared to conventional NOR type CAM assuming a network router application.

Low-energy dissipation as well as high-speed matching are two goals in the design of content addressable memories (CAMs). An efficient matchline (ML) controller is proposed in this work to achieve a low-power hybrid CAM while maintaining acceptable performance for search. This is applied in the implementation of 128×32-bit CAM using 45-nm CMOS technology. Short and fast discharged ML path of the proposed controller makes it possible for the CAM to provide 58.56% and 13.11% improvement in search-speed over a conventional NAND-based CAM and a hybrid-type CAM, respectively. The result of shorter NAND-ML controlling the longer NOR-ML is able to suppress not only mismatched but also partial matched NOR- MLs, so that power is saved during search operation. While the average-power consumption is only 3.93 µW, lesser by 30.69 % than the low-power NAND-CAM, the 32-bit word produces ML state in 3.58 ns search time leading to the improvement in energy-delay by 1.21, 2.16 and 4.95 times from the existed hybrid-type, NOR-ML and NAND-ML CAMs, respectively. Energy metric of proposed design, obtained as 0.17 fJ/bit/search under 1 V supply, is the least among the compared designs.

We have proposed a Hamming distance search CAM (content addressable memory) using neuron MOS transistors. The proposed CAM can compare stored data and a search data in parallel, and find stored data with Hamming distance within a certain range. These functions of the CAM are useful for data management and pattern recognition, etc. In this paper, we analyze the power consumption of the proposed CAM in interrogation operation. The proposed CAM can reduce search current to perform the interrogation operation with lower power consumption than conventional NOR-type CAM's with Hamming distance search functions. Furthermore, the results obtained from these analyses are fully confirmed by HSPICE.