BrainForest: Neuromorphic Multiplier-Less Bit-Serial Weight-Memory-Optimized 1024-Tree Brain-State Classification Processor.

The application of thin ceramic films for the fabrication of MEMS devices enables the extension of their working temperature range up to 600°C, a decrease in heating power consumption, and a very considerable decrease in production cost of sensors and actuators based on this technology. These advantages are very important for the application of gas sensors under harsh environmental conditions, in autonomous and wireless sensor networks. The methods of the fabrication of MEMS platforms for metal oxide semiconductor and thermocatalytic gas sensors, fast thermometers, and flowmeters based on yttria stabilized zirconia (YSZ) and alumina membranes for gas sensors are described. Alumina membranes stable up to 800°C have thickness of about 12 microns and are produced by anodic oxidation of aluminum foil in diluted oxalic acid followed by high-temperature annealing. YSZ membrane with the same thickness is made by slip casting with consequent annealing under mechanic load. Platinum heaters are deposited onto the surface of the membrane by magnetron sputtering through metallic shadow mask. Perfect adhesion of platinum to ceramic material permits us to avoid the application of adhesive sub-layers, and, therefore, improves long-term stability of the heater at high temperature. The sensor chip has a shape of triangle cut by laser beam; the heater meander is located in the vertex of triangle. This approach simplifies the technology of the fabrication of the platform and decreases power necessary for the heating of the sensing layer up to working temperature of 400 – 600°C. It is shown that the application of such triangle shaped membranes permits a decrease in power consumption of the MEMS working at 450°C down to ~ 40 mW at continuous and down to < 1 mW at pulse heating of gas sensor with duty cycle of 1 %. Thermal response time of the microheater is of about 80 ms.

In this paper we have developed a new scheduling algorithm that provides a decrease in dynamic power consumption through achieving components scheduling. The major idea of that algorithm is to amplify the latency of some components whenever it is feasible without negatively influencing the dependency constraints. For that purpose, we have decreased the frequency of the components clocks. Since frequency and power are inter-related, a decrease in frequency value will be followed by a decrease in power consumption. Our algorithm has been tested and has given an interesting gain in dynamic power.

As the usage of internet is increasing day by day, more and more people are now getting connected with the web. In the last few years, internet has become a powerful platform that has changed the way to do a business and the way of communication. The number of users which were using the services of internet in last ten years is becoming double in the number, in every two years. As the number of users is increasing the more storage and new technologies and new platform to develop software are on a huge demand. Then cloud computing came into the picture, which is providing huge storage capacity, on demand self-service, pay according to usage, flexible pricing, resource pooling, software for users and services on their demand which can be accessed anywhere (SaaS), platform to develop new software (PaaS), any hardware which is required for development (IaaS). Now even XaaS i.e. everything as a service (here X is considered as everything, its value can be any) is also coming into the picture. To run one or more than one services or applications together but in their separated space or partition, we need virtual machine. It is refer to the one instance of an operating system (Guest OS). Then Virtualization makes it possible to run many operating systems and applications on the same physical computer at the same time. It makes the physical system energy efficient, as many machines or applications are able to run all together, in a way it consumes less energy. To make the physical system more energy efficient, migration of virtual machine is done, so that we can reduce the energy consumption. VM Migration is used for migration of virtual machine from one PM (physical machine) to another physical machine or host. In this paper, we will discuss about the introduction of cloud computing-its types and topologies; and the main focus would be on energy efficiency using VM migration.

With an emphasis on improving energy efficiency (EE) and lowering power consumption of rapidly growing connected vehicles and infrastructures, Vehicle-to-Everything (V2X) communication is emerging as a fundamental element in the development of smart cities. This paper introduces an innovative reinforcement learning (RL)-based method for dynamic resource allocation within 5G-enabled V2X networks, focusing on EE and minimizing power consumption. The suggested framework adeptly modifies transmission power, and spectrum allocation in real-time, responding to fluctuating traffic patterns and network demands. By facilitating ongoing learning and decision-making, the RL system guarantees optimal resource utilization while preserving high-quality service and low-latency communication. Q-learning is employed to dynamically regulate power levels in urban vehicular scenarios, taking Doppler shift, user mobility, and changing traffic conditions into account. Experimental evaluations demonstrate a substantial decrease in power consumption and an improvement in network efficiency providing a sustainable solution for smart mobility initiatives, promoting the advancement of greener, more reliable, and energy-efficient urban transportation systems.

We consider a power constrained downlink communication scenario where energy efficiency, reliability, and latency take precedence over rate, as in some Internet of Things (IoT) applications. To reduce its receiver power consumption and complexity, we assume that the IoT device has a single RF chain and investigate the finite-resolution analog-to-digital converter (ADC) operation with differential Phase Shift Keying (PSK) modulation. A lower ADC resolution leads to an exponential decrease in power consumption, while adopting differential PSK enables the use of a low-cost detector with no channel state information (CSI) or carrier phase recovery circuitry. Our main goal in this article is to compare, both analytically and numerically using representative IoT system design parameters, the receiver energy efficiency of the proposed differential PSK system with a coherent PSK system that uses estimated CSI under reliability and latency constraints in Rayleigh slow-fading and ADC quantization distortion conditions. To mitigate the ADC finite-resolution effects without requiring CSI at the receiver or transmitter, we propose and analyze a PSK differentially-modulated Alamouti space-time block transmission scheme with only two RF chains at the transmitter while still restricting the IoT device to have a single RF chain. Our results demonstrate that in the considered low-rate, and outage and latency-constrained scenario with stringent power consumption requirements, differentially-modulated Alamouti transmissions to a single RF-chain IoT device with a low-resolution ADC is an attractive choice in terms of receiver energy efficiency, reliability, and transmission latency.

Tremendously increasing bandwidth demands on the Internet require high transmission capacity and reliable end-to-end connections which are offered by optical WDM networks. Huge bandwidth demands of the applications cause rising energy consumption at the optical cross-connects which contributes a significant portion of the total electricity consumption. In this paper, we study the availability design of optical WDM networks in an energy-aware perspective. We propose Power-Aware Reliable Design (PARD) for optical networks which is mainly based on two-step multi-hop lightpath bypass concept aiming to provision survivable demands with minimized power consumption. Through simulations, we show that our proposed approach, PARD can guarantee high availability levels for the demands with a significant decrease in power consumption when compared to a lightpath non-bypass availability maximization design. Moreover, it is also shown that employment of PARD is more fair than a lightpath non-bypass availability maximization approach in terms of deviation of per-node power consumption. We also show that increasing the spare capacity at the backup virtual links causes further decrease in power consumption while leading to a slight decrease in connection availability. Furthermore, we present that migrating to greener resources further improves the CO 2 emissions of PARD significantly.

Decreasing power consumption with energy efficient data aware strategies

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreased power consumption by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using Interpolation technique for purpose of promoting the performance as well as decreasing the class of Chip. The simulation results indicate that the power consumption for Interpolation technique was decreased by approximately 5% compared to the proposed method. On the other hand, we compare the results of the proposed convector with those of convertors frequently referred in other studies. The results show that the power consumption is considerably decreased, using the proposed method.

Objective To analyze neural activity of in rat prefrontal cortex with the use of nonnegative matrix factorization with sparseness constrains (NMFs) as a methodology and to study how to express neural ensemble with higher precision during working memory task.Methods Experiment data were obtained from neural population activity in the period 5 s before and after the working memory event.From the zero point,the neuronal firing times were binned in windows of 200 ms with 50 ms overlapping.The normalized neuronal bin-count matrix is decomposed by NMFs into mixing matrix and source component matrix with sparseness constraints.Meaningful components were extracted to reconstruct the input by an inverse of NMFs transform.Results By analyzing the ten groups of data from 2 rats,with the numbers of the sparse sources of 10 and 15 respectively,explicit neural ensembles with the feature components were obtained in the sparse reconstructed activity.Comparing to rate coding,the spatiotemporal location of neural ensemble was more precisely detected.Conclusion The working memory information is encoded with neural ensemble activity.NMFs could find the sparse firing pattern robustly in neuron population activity.NMFs removes much redundancy and demonstrate the possibility to express neural ensemble with higher precision compared with rate coding,which would be helpful to infer correlations between cortical firing pattern and working memory event. Key words: Non-negative matrix factorization with sparseness constrains; Neural firing activity; Neural ensemble; Working memory event

Deep neural networks (DNNs) have recently achieved remarkable performance in a myriad of applications, ranging from image recognition to language processing. Training such networks on graphics processing units (GPUs) currently offers unmatched levels of performance; however, GPUs are subject to large-power requirements. With recent advancements in high-level synthesis (HLS) techniques, new methods for accelerating deep networks using field programmable gate arrays (FPGAs) are emerging. FPGA-based DNNs present substantial advantages in energy efficiency over conventional CPU- and GPU-accelerated networks. Using the Intel FPGA software development kit (SDK) for OpenCL development environment, networks described using the high-level OpenCL framework can be accelerated targeting heterogeneous platforms including CPUs, GPUs, and FPGAs. These networks, if properly customized on GPUs and FPGAs, can be ideal candidates for learning and inference in resource-constrained portable devices such as robots and the Internet of Things (IoT) edge devices, where power is limited and performance is critical. Here, we introduce GPU- and FPGA-accelerated deterministically binarized DNNs, tailored toward weed species classification for robotic weed control. Our developed networks are trained and benchmarked using a publicly available weed species dataset, named DeepWeeds, which include close to 18 000 weed images. We demonstrate that our FPGA-accelerated binarized networks significantly outperform their GPU-accelerated counterparts, achieving a>7-fold decrease in power consumption, while performing inference on weed images 2.86 times faster compared to our best performing baseline full-precision GPU implementation. These significant benefits are gained whilst losing only 1.17% of validation accuracy. In this paper, this is a significant step toward enabling deep inference and learning on IoT edge devices, and smart portable machines such as agricultural robots, which is the target application.

In this paper, we focus on the problem of designing an energy efficient MAC protocol for wireless sensor networks and propose a novel scheme, named TEEM (traffic aware, energy efficient MAC). Inspired by the S-MAC protocol, probably the most well-known sensor MAC scheme for energy efficiency, the proposed TEEM is also based on the concept of 'listen/sleep modes cycle'. However, unlike S-MAC where the duration of listen and sleep modes are fixed, our TEEM protocol makes these durations adaptive by utilizing the 'traffic information' of each node, and hence achieves a significant decrease in power consumption. Through implementation in motes sensors, the presented TEEM is evaluated and compared to S-MAC as well as the IEEE 802.11-like protocols.

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional static random access memory (SRAM) due to its high-density, low-leakage, and inherent two-ported operation, yet its dynamic nature leads to limited retention time and calls for periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances lead to accelerated data integrity deterioration. The emerging approximate computing paradigm utilizes the inherent error-resilience of different applications to tolerate some errors in the stored data. Such error tolerance can be exploited to reduce the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption at the cost of an increase in cell failure probability. In this paper, we present the first fabricated and fully functional GC-eDRAM in a 28-nm bulk CMOS technology. The array, which is based on a novel mixed- $V_{T}$ four-transistor (4T) gain cell with internal feedback (IFGC) optimized for high performance, features a small silicon footprint and supports high-performance operation. The proposed memory can be used with conservative (i.e., 100% reliable) computing paradigms, but also in the context of approximate computing, featuring a small silicon footprint and random access bandwidth. Silicon measurements demonstrate successful operation at 800 MHz under a 900-mv supply while retaining between 30% and 45% lower bitcell area than a single-ported six-transistor (6T) SRAM and a two-ported six-transistor (8T) SRAM in the same technology.

Enhancement of Performance and Energy Efficiency of Air Conditioning System Using Evaporatively Cooled Condensers

Energy efficiency based multi-relay selection and power allocation in OFDM cooperation networks

It is important to study the application of alternative carbon reductants for industrial silicon smelting to reduce consumption of carbonaceous reducing agents, electricity, and CO2 emissions during silicon production. In this study, an industrial experiment was carried out in an 8 MVA submerged arc furnace using waste carbon material in place of approximately 20% partial reducing agents. The system was analyzed for silicon yield, power consumption, overall energy efficiency, CO2 emissions, and the utilization rate of carbonaceous materials. The system improved the efficiency of carbonaceous materials and decreased power consumption using alternative carbon reductants. The results have showed that use of waste carbon materials reduced carbon emissions per ton silicon by more than 19.14% and specific CO2 emissions decreased to 0.865 t.