Abstract
Even though spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is considered to be a leading candidate for next generation memory, designing a sensing circuit (SC) that achieves sufficient read yield is challenging because of the increased process variation, decreased read current (I<SUB>read</SUB>), and small tunnel magnetoresistance (TMR) ratio. In this paper, a novel body-biasing-based latch offset cancellation SC (BBLOC-SC) that is capable of canceling the offset voltage caused by the latch sense amplifier is proposed. Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed BBLOC-SC achieves a much higher read yield compared to the state-of-the-art SCs, regardless of TMR and I<SUB>read</SUB>.
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