Abstract
The metal in the blanket tungsten process for microelectronic interconnects is deposited in via holes or trenches of sub-micron radius/width and depths of the order 2 μm. This process is usually isothermal, based on chemical vapor deposition. However, the resulting concentration gradients along the depth of the via promote formation of a void (keyhole) in the feature, unless processing is at low temperatures and hence, for longer duration. Using process modeling, the feasibility of the two approaches are investigated that rely on a non-isothermal process, which are equally fast and reduces the volume of the keyhole defect. In the first, application of a thermal gradient is examined, which can mitigate the tendency to form keyholes. However, the process conditions require excessive gas flow rates. In another, continuous cooling of the substrate while deposition occurs simultaneously is examined. The method based on continuous cooling appears more feasible in optimizing between keyhole size and process time.
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