Binarized Neural Network Based On FPGA To Realize Handwritten Digit Recognition

Abstract

We trained a binarized neural network (BNN) which can be used for handwritten digit recognition on software, and implemented this BNN on the FPGA using software training parameters without the help of high-level synthesis (HLS). This BNN contains an input layer, two convolutional layers, two pooling layers, a fully connected layer and an output layer. The first convolution layer contains 10 convolution kernels, each of which has a size of $5^{ \ast} 5$ . Each convolution kernel uses 25 arithmetic units to calculate in parallel, the calculation of 10 convolution kernels is also parallel. The size of the convolution kernels in the second convolutional layer is $3^{ \ast} 3$ , the input and output channels are 10, we use 900 XNOR gates for calculation here. Compared with the traditional CNN, it does not need to consume DSP resources and requires less storage space for the parameters. And the power consumption obtained by Quartus ii software of this BNN is 0.136 W. The time to identify a picture is $18 \mu \mathrm{s}$ , and the accuracy rate is 85% without the batch normalize (BN) layer.