Behavioral design of approximate arithmetic systems for reliable computing

Abstract

Despite the advances in semiconductor technologies and development of energy-efficient design techniques, the overall energy consumption of computer systems is still rapidly growing at an alarming rate in order to process an ever-increasing amount of information. As computer systems become pervasive, they are increasingly used to interact with the physical world and process a large amount of data from various sources. Energy-efficiency has become the paramount concern in design of computing systems. At the same time, as the computing systems become increasingly embedded and mobile, computational tasks include a growing set of applications that involve media processing, recognition, and data mining. A common characteristic of the above class of applications is that often a perfect result is not necessary, and an approximate or less-than-optimal result is sufficient. As one of the most promising energy-efficient computing paradigms, approximate computing has gained a lot of research attention in the past few years. This dissertation focuses on the approximate arithmetic circuit design. First, a novel 2-D approximate Convolver was designed. The convolution can be conduct approximately by reducing the bit-width based on the image quality requirement (as the metric of PSNR). The error analysis is performed to substantiate the simulation results; an error compensation scheme is introduced to improve the accuracy in computation. Second, a profiling-based error compensation scheme is explored. A so-called Padding is applied to the computation result to shift the overall error distribution based on the statistic profiling of the input pattern. This novel scheme is applied basic arithmetic units as adder, multiplier and divider. The error analysis is conducted verifying the simulation results. The circuit metrics as power, delay and area are measured for comparison with exact unit and other approximation unit. Third, the Approximate Redundancy scheme is discussed. Two approximate voting schemes are proposed. The proposed IDMR and ITDMR schemes improve the power dissipation and tolerance to variations compared to a traditional TMR. Besides, the Reduced Precision Redundancy MAC scheme is also proposed to reduce the overhead while still being able to correct the largest errors by studying on the properties of signed integer multiplication.