Bed of nails - 100 microns pitch wafer level interconnections process

Abstract

The rapid advances in IC design and fabrication continue to challenge the electronic packaging technology, in terms of fine pitch, high performance, low cost and better reliability. In the near future, the demands for higher I/O count per integrated circuit (IC) chip increases as the shift towards the nano ICs with feature size less than 90nm. To meet the above requirements, the chip-to-substrate interconnection technologies with less than 100/spl mu/m pitch are required. Currently, the CTE mismatch between Si chip and substrate and assembly yield of such fine pitch interconnections serves as the biggest bottle neck issue. In this work a simple copper column based bed of nails-wafer level interconnects showing greater potentials in meeting some of these requirements for next-generation packaging is reported. The process development of fabricating the copper columns with various height and solder deposition on to the tip of the column is reported. This technology has been developed to meet fine pitch of 100 microns and high density interconnections. The development of a test chip demonstrator of 10 /spl times/ 10mm/sup 2/ with 3338 I/Os designed and fabricated for optimizing the process and the board level reliability test with out underfill performed under temperature cycling at range of -40/spl deg/C to 100/spl deg/C are also presented.