Abstract
A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si3N4/Al2O3/Si3N4 (NAN) was adopted as a trap layer in place of single Si3N4 layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si3N4 trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
