Avalanche ruggedness and reverse-bias reliability of SiC MOSFET with integrated junction barrier controlled Schottky rectifier

Abstract

A process and a scalable structure were used to implement the SiC MOSFET with integrated junction barrier controlled Schottky diode (JMOS) without area penalty. The JMOS could provide similar on-resistance and drain-source breakdown voltage with the same chip size as the standard double-implanted MOSFET (DMOS). The ideal factor and Schottky barrier height of integrated Schottky diode were 1.13 and 1.22eV for 650V JMOS and 1.11 and 1.27eV for 1200V JMOS. The diode forward voltage drop of JMOS were lower than DMOS when the diode forward current were smaller than 44A for 650V JMOS and 58A for 1200V JMOS. The reverse recovery charge of 650V and 1200V JMOS at 150°C were 22% and 53% lower than corresponding DMOS. The peak reverse recovery current of 650V and 1200V JMOS were 26% and 40% lower than corresponding DMOS. The output capacitance of JMOS were also lower than DMOS. The avalanche energy (Eas) of 650V and 1200V JMOS were 1682mJ and 1270mJ, smaller than the corresponding DMOS, but a 17.2 J/cm2 Eas is still superior to silicon counterparts. The results of diode forward current stress, diode surge current test and 1000 hours high temperature reverse bias test demonstrated that JMOS is reliable.