Author retrospective for characterizing processor architectures for programmable network interfaces

Abstract

Our investigation into architectural support for networking tasks began in late 1998, and it began with something of a coincidence. Fiuczynski was an active graduate student participant in the SPIN project at UW [2,3]. He had been writing a SPIN driver for a high-speed network interface card (NIC), and visited Crowley (at the time, a graduate student investigating the relationships between processor & memory architectures and desktop computer applications [4]) one afternoon to discuss the NIC's processor. Had either Fiuczynksi or Crowley been out of the office on that particular day, it is not clear that this collaboration would have emerged. As it happened, both were in the office that day and the NIC processor was very interesting: a dual-core MIPS-like processor built specifically for the NIC. In ensuing discussions, it became clear that-despite the simplicity of its instruction set and microarchitecture-the NIC processor was as a whole more interesting than the much larger and complex x86 processor of the host system. It was more interesting because, as a dual-core processor, it was different and in no way an incremental improvement upon the deeply pipelined CPUs that dominated computing at the time. (They still dominate PCs and servers, of course, but mobile, graphics and embedded chips represent a huge swath of relevant computing platforms today.) It represented evidence of a combination of commercial and technical justification for designing a new and different processor to handle networking tasks.