Area‐time complexity on a vlsi model with boundary layout assumption

Abstract

AbstractIn the VLSI circuit, the area occupied by the circuit and the time required for computation are important measures of evaluation. Thompson, Brent and Kung have proposed a VLSI model to evaluate the VLSI circuit by the area A and the computation time T. It is an important problem to examine the change of the area and the computation time when a certain practical assumption is imposed on the VLSI model. This paper shows that when an assumption that the input and the output are connected at the boundary of the circuit (called boundary‐layout assumption) is imposed on the VLSI model, relations AT = ω(max(n, m)) and ATa = ω(max(n, m)[max(log N, log M)]a) (α > 1) are produced for the nontrivial class of n‐input, m‐output logic functions. Above, N is the maximum of N1, …, Nm, where Ni is the number of inputs on which the ith output depends, and Mj is the maximum of M1, …, Mn, where Mj is the number of outputs which depends on the jth input. When the boundary‐layout assumption is not imposed, ATα = ω(max(n, m){max(log N, log M)}α‐1) (α ≥ 1) holds. Consequently, for this class of functions, the boundary‐layout assumption properly affects ATα (α ≥ 1). It is shown also by an actual example that there exist functions which achieve the lower bounds.