Abstract

In this paper, we propose an area-efficient short-time Fourier transform (STFT) processor that can perform time–frequency analysis of non-stationary signals in real time, which is essential for voice or radar-signal processing systems. STFT processors consist of a windowing module and a fast Fourier transform processor. The length of the window function is related to the time–frequency resolution, and the required window length varies depending on the application. In addition, the window function needs to overlap the input data samples to minimize the data loss in the window boundary, and overlap ratios of 25%, 50%, and 75% are generally used. Therefore, the STFT processor should ideally support a variable window length and overlap ratio and be implemented with an efficient hardware architecture for real-time time–frequency analysis. The proposed STFT processor is based on the radix-4 multi-path delay commutator (R4MDC) pipeline architecture and supports a variable length of 16, 64, 256, and 1024 and overlap ratios of 25%, 50%, and 75%. Moreover, the proposed STFT processor can be implemented with very low complexity by having a relatively lower number of delay elements, which are the ones that increase complexity in the most STFT processors. The proposed STFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using a standard cell library in a 65 nm CMOS process. The proposed STFT processor results in logic gates of 197,970, which is 63% less than that of the conventional radix-2 single-path delay feedback (R2SDF) based STFT processor.

Highlights

  • Short-time Fourier transform (STFT) is a time–frequency analysis technique for non-stationary signals

  • To verify that the proposed short-time Fourier transform (STFT) processor architecture is efficient in terms of hardware complexity, we implemented STFT processors using radix-2 single-path delay feedback (R2SDF), radix-4 multi-path delay commutator (R4MDC), and the proposed architectures

  • R4MDC-based STFT processor and by 63% compared with the R2SDF-based STFT processor

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Summary

Introduction

Short-time Fourier transform (STFT) is a time–frequency analysis technique for non-stationary signals. Depending on the type of window used, the STFT processor should be capable of changing the overlap ratio to the one that minimizes data loss. Implemented an STFT processor that uses several SDF FFT processors in parallel to support a high overlap ratio, but this increases complexity [18]. Srinivas et al implemented the STFT processor as a single SDF FFT processor and reused the FFT calculation results to reduce hardware area and latency [19] This STFT processor can only use a rectangular window and supports a 50% overlap only. In this paper, we propose an STFT processor that provides a 0/25/50/75% variable overlap ratio to minimize data loss depending on the type of window used and 16/64/256/1024-point variable window lengths to support various time–frequency resolutions.

STFT Algorithm and Hardware Architecture
Variable Overlap Ratio of the Proposed STFT Processor
Hardware Architecture of the Proposed STFT Processor
Implementation Results
Conclusions
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