Abstract
In this study by using the modified Wallace tree multiplier, an error compensated adder tree is constructed in order to round off truncation errors and to obtain high through put discrete cosine transform design. Peak Signal to Noise Ratio (PSNR) is met efficiently since modified Wallace Tree method is an efficient, hardware implementable digital circuit that multiplies two integers resulting an output with reduced delays and errors. Nearly 6% of delays and around 1% of gate counts are reduced. The number of look up tables consumed is 2% lesser than that of the previous multipliers. Thus an area efficient discrete cosine transform is built to achieve high throughput with minimum gate counts and delays for the required Peak Signal to Noise Ratio when compared to the existing DCT’s.
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