Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevicecircuit interconnect

Abstract

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplanecircuits is emerging as one viable option to sustain Moore’s law after the CMOS scalinglimit is reached. One main design challenge in such hybrid nanoelectronics is the interfacebetween the highly dense nanowires in nanodevice crossbars and relatively coarsemicrowires in the CMOS domain. Such an interface can be realized through a logic circuitcalled a demultiplexer (demux). In this context, all the prior work on demux design uses asingle type of device, such as resistor, diode or field effect transistor (FET), to realizethe demultiplexing function. However, different types of devices have their ownadvantages and disadvantages in terms of functionality, manufacturability, speed andpower consumption. This makes none of them provide a satisfactory solution.To tackle this challenge, this work proposes to combine resistor with FET toimplement the demux, leading to the hybrid resistor/FET-logic demux. Such hybriddemux architecture can make these two types of devices complement each otherwell to improve the overall demux design effectiveness. Furthermore, due to theinevitable fabrication process variations at the nanoscale, the effects of resistorconductance and FET threshold voltage variability are analyzed and evaluated based oncomputer simulations. The simulation results provide the requirement on thefabrication process to ensure a high demux reliability, and promise the hybridresistor/FET-logic demux an improved addressability and process variance tolerance.