Architecture and Programming of Parallel Video Signal Processors

Abstract

The chapter the architecture of two generations of VSPs developed, illustrates the concepts and implementation of the dedicated programming tools, and describes some applications and results associated with them. Programmable video signal processor ICs (VSPs) have been developed for the real-time processing of digital video signals. These processors are supported by dedicated programming tools. A large number of applications have been developed with boards containing several of these processors. The implementation of digital video processing requires a high computing power and a high communication bandwidth because the sampling rates for video signals are in the order of a few to several tens of MHz. Video signal processing can be done with a limited resolution in the number of bits. Currently, two implementations of the general architecture exist: VSP1 and VSP2. A single chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is done with signal flow graphs (SFGs). These SFGs can conveniently express multi-rate algorithms. These algorithms are mapped onto a network of processors. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications.