Approximation Logic for Multiplication Through Partial Product Perforation

Abstract

The partial product perforation or truncation methods for approximate multiplication, though have well defined error boundaries are not independent of the number of bits in the number being perforated. In this paper the partial product perforation from Most Significant Bit (MSB) technique is proposed. In this method the error boundaries are well defined and are independent of the number of bits in the number which is being perforated. As the error boundaries are well defined, this technique can be put to practical use in the applications which are error tolerant. This technique optimizes the generation of partial products as per the error tolerance of the application. As the partial product generation is optimized, the number of full adders being used is also optimized and hence the power consumption and delay are also optimized. A 32 bit multiplier for 1% error tolerance, the proposed method gives 75% and 35% reduction in power and delay respectively as compared to the accurate multiplier.