Approximate Adder Circuits: A Comparative Analysis and Evaluation

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

As an important arithmetic module, the adder plays a key role in determining the speed and power consumption of a digital signal processing (DSP) system. The demands of high speed and power efficiency as well as the fault tolerance nature of some applications have promoted the development of approximate adders. This paper reviews current approximate adder designs and provides a comparative evaluation in terms of both error and circuit characteristics. Simulation results show that the equal segmentation adder (ESA) is the most hardware-efficient design, but it has the lowest accuracy in terms of error rate (ER) and mean relative error distance (MRED). The error-tolerant adder type II (ETAII), the speculative carry select adder (SCSA) and the accuracy-configurable approximate adder (ACAA) are equally accurate (provided that the same parameters are used), however ETATII incurs the lowest power-delay-product (PDP) among them. The almost correct adder (ACA) is the most power consuming scheme with a moderate accuracy. The lower-part-OR adder (LOA) is the slowest, but it is highly efficient in power dissipation.

Low power dissipation in approximate arithmetic circuits has laid the foundation for area-efficient computational units for error resilient applications like image and signal processing. This paper proposes two novel low power high speed architectures for approximate 4:2 compressor that can be employed in multipliers for partial product summation. The two designs presented ([Formula: see text] and [Formula: see text]) have Error Distance (ED) of [Formula: see text] and Error Rate (ER) of 25%. The proposed [Formula: see text] and [Formula: see text] are able to achieve reduction in power and delay by (62.50%, 47.67%) and (83.13%, 60.20%), respectively, in comparison with the exact 4:2 compressor. To verify the effectiveness of the design, the proposed architectures are used to implement [Formula: see text] Dadda multiplier. The equal number of errors in positive and negative directions in the proposed designs aid in reducing the Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of the multiplier. Multiplication of images and two-level decomposition of 2D Haar wavelets are implemented using the designed Dadda multiplier. The efficiency of the image processing applications is measured in terms of Mean Structural Similarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR) and an average of 0.98 and 35[Formula: see text]dB, respectively, is obtained, which are in the acceptable range. In addition, a Convolutional Neural Network (CNN)-based LeNet-1 Handwritten Digit Recognition System (HDRS) is implemented using the proposed compressor-based multipliers. The proposed compressor-based architectures are able to achieve an average accuracy of 96.23%.

Approximate arithmetic circuits have gained prominence in modern computing systems due to their ability to trade accuracy for improved performance and energy efficiency. However, their susceptibility to stealthy Trojan attacks poses a significant security concern. This work analyzes Trojan attacks on approximate circuits, focusing specifically on approximate adders and multipliers. We propose SATGuard, a boolean satisfiability (SAT)-based methodology to identify Trojan activating inputs (TAIs) for all approximate adder and multiplier families. We also claim that TAIs for approximate circuits are analogous to test input patterns for accurate circuits. Subsequently, we propose design-specific countermeasures to safeguard approximate circuits. The proposed countermeasures nullify the Hardware Trojan Horse (HTH)-based accuracy degradation, thus upholding the application-level accuracy requirements. We conduct experiments where potential Trojans are implanted into various approximate adders and multipliers. We evaluate their impact on the error metrics and the quality of results in real-world applications such as image processing and deep neural networks (DNNs). Our findings demonstrate that the proposed methodology successfully reverses the HTH-based accuracy degradation by 99.4%, and 99.8% in approximate adders and multipliers, respectively. This improvement is achieved with an average area overhead of 5.3% and a power-delay-product overhead of 7.6% in approximate adders and 1.7% and 1.9% in multipliers, respectively.

Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications

This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65-nm CMOS technology, the proposed design also achieves 21% and 12% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.

This paper presents a new approximate adder design to improve the computation accuracy of the conventional error tolerant adder by leveraging a carry prediction technique with a sum generator. The proposed carry speculation scheme exploits inputs from a single bit position and effectively increase the bit width of the accurate addition. Implemented in a 65-nm CMOS technology, the proposed approximate adder is up to two times faster than, and twice as power efficient as, the traditional adders. Compared to the other approximate adders considered in this paper, the proposed adder achieves up to 3.7%, 15.5%, 79.9% and 79.9% reductions in the error rate (ER), mean relative error distance (MRED), mean error distance (MED) and normalized MED (NMED) respectively, at an extra cost of merely 4% to 6% in area, delay, and power. In addition, the proposed adder offers a good tradeoff between power/energy and accuracy and improves on power/energy-NMED products by up to 46%, outperforming other approximate adders.

This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. Particularly, the proposed carry prediction technique can reduce a prediction error rate by up to 75% compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). Our experimental results show that the proposed adder improves the normalized mean ED (NMED) and mean relative ED (MRED) by up to 91.4% and 98.9%, respectively, compared to the other approximate adders. Importantly, an excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Specifically, the proposed adder achieves up to 95.7%, 91.1%, and 93.2% reductions of the power-NMED, energy-NMED, and area-delay product (ADP)-NMED products, respectively, compared to the other adders. Our adder enhances the power-, energy-, and ADP-MRED products by up to 99.4% compared to the others. In particular, the figure of merit (FoM) considering both hardware and accuracy of the proposed adder is up to 99.95% smaller than that of the other approximate adders considered herein. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.

High-performance, energy-efficient, and memory-efficient FIR filter architecture utilizing 8x8 approximate multipliers for wireless sensor network in the Internet of Things

Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.

Approximate computing has emerged as a new paradigm for high-performance and energy-efficient design of circuits and systems. For the many approximate arithmetic circuits proposed, it has become critical to understand a design or approximation technique for a specific application to improve performance and energy efficiency with a minimal loss in accuracy. This article aims to provide a comprehensive survey and a comparative evaluation of recently developed approximate arithmetic circuits under different design constraints. Specifically, approximate adders, multipliers, and dividers are synthesized and characterized under optimizations for performance and area. The error and circuit characteristics are then generalized for different classes of designs. The applications of these circuits in image processing and deep neural networks indicate that the circuits with lower error rates or error biases perform better in simple computations, such as the sum of products, whereas more complex accumulative computations that involve multiple matrix multiplications and convolutions are vulnerable to single-sided errors that lead to a large error bias in the computed result. Such complex computations are more sensitive to errors in addition than those in multiplication, so a larger approximation can be tolerated in multipliers than in adders. The use of approximate arithmetic circuits can improve the quality of image processing and deep learning in addition to the benefits in performance and power consumption for these applications.

In recent times, approximate computing techniques have emerged as a popular computing paradigm that can significantly minimize consumption of resources at the cost of bounded loss in accuracy of results. More specifically, approximate arithmetic circuits such as addition and multiplication architecture have been widely deployed to benefit image processing, machine learning and other error-resilient applications. However, a major drawback attributed with approximate architectures is that the results generated by them are probabilistic in nature. This indeterminism in input-output characteristics results in security breaches during post-silicon validation. In other words, the relaxation in precision may lower the standard of testing metrics, thus making block-based approximate designs vulnerable to security attacks. This work proposes a digital Hardware Trojan Horse (HTH) that renders approximate adder circuits inefficient. The proposed attack exploits the probabilistic nature of approximate designs to successfully implant the HTH. The presented HTH replaces the original sum-bit generation logic in a 1-bit full adder widely present as a building block in a major class of block-based low latency approximate adders. Experimental results showcase that insertion of HTH in state-of-the-art approximate adders can reduce the end applications accuracy by 2–13%, and 24–31% when Trojan is inserted at Least significant Bit side (LSBs) and Most Significant Bit (MSBs) respectively. Our proposed Trojan does not add significant area overhead upon successful insertion. Additionally, the obtained results also signify that block-based low latency approximate adders with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> number of blocks are N/2 times more vulnerable to security attacks than their binary segmentation counterparts. Experimental results also demonstrate that the impact of a digital HTH may be considered to be relatively mild in exact computing designs, it proves to alter the intended behaviour of approximate circuits when tested across real time applications such as machine learning and image processing.

In recent years, many approximate arithmetic circuits have been proposed to exploit available error resiliency in a wide set of applications. Approximate adders, multipliers, and dividers reduce their original delay, area, power, or energy, as the accuracy of their results is lowered. Due to the diversity of these approximate units and their potential configurations, selecting one that properly fits t o a specific design requires to dispose with a vast number of such units already implemented and characterized. Even to propose new approximate arithmetic circuits, it is required to have existing ones available to perform comparisons. In this paper, we present AUGER, a tool to generate and characterize state-of-the-art approximate arithmetic circuits, providing their RTL implementation and a functional model. We validate our tool by presenting examples of its usage and performing analysis with results it produces. AUGER is released as an open-source contribution.

Approximate adders have become a focus of approximate circuit design. However, there has been a lack of appropriate methods to evaluate their reliability. The existing analytical methods for accurate circuits cannot be applied to approximate circuits directly, and the Monte-Carlo simulation is time-consuming. Some metrics such as worst-case error, error distance, mean error distance and normalized error distance have been used to describe the reliability characters and arithmetic performance of approximate circuits, but they cannot directly calculate the reliability. This paper presents two methods for approximate adders reliability estimation based on the probabilistic transfer matrix (PTM) model. The first method takes the sum of the probabilities of all acceptable outputs as the probability of acceptable result corresponding to each input. The second method calculates the probability of acceptable result according to the deviation between the acceptable output and exact output. The reliability of approximate adders is calculated by combining the probabilities of the input vectors and those of the corresponding acceptable results. Experimental results demonstrate the validity and accuracy of the proposed methods.

This paper proposes an approximate adder that employs a novel carry speculation scheme to enhance the computation precision of the existing error tolerant adder (ETA) designs with extremely little hardware overhead. The proposed carry prediction technique leverages two input bits to increase the prediction accuracy while the conventional ones do only one bit. This leads to a reduction of the carry prediction error rate from 25% to 18.75%. Compared to the existing ETA design, the proposed adder reduces normalized mean error distance (NMED) and mean relative error distance (MRED) by up to 10% and 28%, respectively, at the cost of only a two-input OR gate. Moreover, the proposed design outperforms the conventional ETAs when jointly evaluating hardware cost and computation accuracy. Specifically, the new design allows 11% and 17% reductions of area-power-NMED and power-NMED products, respectively, compared to the traditional ETA.