Abstract
In one-way microprocessor, the program code is executed at the maximum (ideal) rate of one instruction per cycle. In practice, due to the occurrence of branch instruction, this rate is less than 1. Superscalar architecture, when applied to a 32-bit RISC microprocessor, enables the handling of two instructions in a single machine cycle. To further increase the processing speed, the out-of-order execution is also applied to process an instruction that its operands are ready. As a result, the microprocessor which can complete two instructions per cycle is obtained.
Highlights
We show how to apply superscalar technique to a 32-bit RISC microprocessor (MCU) to enable a simultaneous processing of multiple instructions
When all operands of instruction are ready, operator will be executed in the Execute stage and the calculation result is saved into the Reorder buffer (ROB)
When instructions are already in the cache, the 2 consecutive instructions are put to the Decode in a cycle
Summary
We show how to apply superscalar technique to a 32-bit RISC microprocessor (MCU) to enable a simultaneous processing of multiple instructions. The maximum number of instructions is 2. The out-of-order execution is incorporated for more efficient use of hardware resources. An instruction is executed immediately when its operands are ready. A branch prediction block with high accuracy is indispensable to reduce waste in the case when branch instructions exist
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