Application of principal component analysis based effective digital predistortion technique for low-cost FPGA implementation

Abstract

This article investigates the issue of low-cost digital predistortion (DPD) implementation in fixed-point field programmable gate array (FPGA) by considering the bit-resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit-resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16-bit fixed-point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class-AB and ZX60-V63+ power amplifiers using wide code-division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak-to-average-power ratio (PAPR) around 9.895 and 11.92 dB, respectively.