Analysis, Simulation and Design of Ternary Logic Circuits Based on CNTFETs in Verilog‐A

This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.

This paper attempts to compare ternary and binary logic gate design using CMOS and carbon nanotube (CNT)-FETs technology. Ternary logic is an effective approach over the default binary logic design technique because it allows to define one more voltage level which is VDD/2 and it also allows a circuit to be simple in design and energy efficient due to its property of reduction in circuit overhead such as interconnects and chip area. A CMOS and CNTFET-based ternary logic gates and arithmetic circuit design has been proposed to implement and compare binary and ternary logic design based on CMOS and CNTFET. The main objective is to compare the CMOS and CNTFET results and verify the advantages of CNTFET technology. The proposed CNTFET technique combined with ternary logic provides an usable performance, improved speed and reduces propagation delay characteristics in circuit such as inverter and decoder. Simulation results of proposed designs using H-SPICE are observed and shown that the proposed ternary logic gates consume significant less delay than the CMOS gates implementations. In realistic digital application, the proposed design of ternary logic compared with binary logic results in over 95% reductions in terms of the consumption of propagation delay.

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

This paper presents a novel CNTFET based design of ternary logics gates where all three ternary logics including standard, positive and negative ternary logic (ST, PT and NT) outputs for each gate are obtained from one structure and are interchangeable through some control inputs. Ternary logic overpowers the conventional binary logic in simplicity and energy efficiency as it reduces number of interconnects and chip area. In this paper design of ternary inverter, buffer, NAND, AND, NOR, OR, XOR and XNOR gates are presented where a unique feature of conversion between ST, PT, NT logic through a single output is being introduced. Besides a single logic gate is designed for a particular logic function and its complement combining both ternary and binary logic gate design technique. The proposed designs utilize the unique property of CNTFET, such as assigning the required threshold voltage value of the FET by changing the diameter of the carbon nanotube (CNT) through its chiral vector values which is very useful in designing multiple- valued logic (here ternary logic). The proposed circuits are simulated using Synopsys HSPICE with 32 nm CNTFET model provided by Stanford University and in each case average power values and propagation delays are duly noted. The effects of variation in some process parameters like channel length, dielectric oxide thickness and number of carbon nanotubes also have been discussed.

This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular we propose the design of NOR/NAND gates and of a Decoder, all in ternary logic. The main novelty is that in this paper all simulations are performed in Verilog-A, avoiding so the problems presented in SPICE. At last we show that the proposed ternary logic gates consume significantly lower power and delay time than the previous CNTFET gates implementations.

Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

This paper presents a design of ternary magnitude comparator based on the CNFET (Carbon Nanotube Field Effect Transistor) ternary logic gates. Ternary logic is a promising alternative to conventional logic design because of its energy efficiency. This energy efficiency is achieved due to the reduced circuit overhead for ternary logic when compared to the conventional binary logic. The comparator design is based on prefix based design and combines ternary and binary logic gates for optimized implementation. The proposed comparator has been implemented and simulated using SPICE. Simulations results indicate that the proposed 1-bit comparator consumes 0.65μW power and has a delay of 21ps. The simulation results for comparators with different operand lengths are also presented.

A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other designs, introduced before, is the elimination of the static power dissipation, which is very important in nano scale CMOS and leads to less power consumption. The proposed design has been simulated, using Synopsys HSPICE tool with 90nm CMOS technology. The simulation results demonstrate the superiority of the presented design with respect to other conventional designs in terms of power consumption and performance.

Since inception, CMOS logic is considered for implementation of only binary logic. As the circuit complexity is increasing, the interconnection in binary occupies large area on a VLSI chip and thus, degrading the performance of binary. Hence the non binary higher radix logic which is called as multi valued logic (MVL) is considered as solution to this issue. A ternary logic or a three-valued logic is considered as the best radix of several MVL systems. In this paper, the designs of ternary logic circuits are proposed based on single power supply voltage. The proposed ternary logic gates are useful in designing the ternary logic circuits. The proposed designs are based on the use of only enhancement type MOSFETS so that it can be implemented with recent CMOS technology. The design of a set of inverters and basic ternary logic gates is proposed. The transistor count in the basic ternary gates is being reduced thereby improving component density. The proposed GATES are designed & simulated with the help of Microwind EDA tool & can be implemented at its layout side using VLSI CMOS technology.

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

Boolean logic devices play a key role in both traditional and nontraditional molecular logic circuits. This kind of binary logic, in which each bit is coded by (0, 1), has only two output states—on or off (or high/low). Because of the finite computing capacity and variation, it is facing challenges from multivalued logic gates while processing high-density or uncertain/imprecise information. However, a low-cost, simple, and universal system that can perform different multivalued logic computations has not yet been developed, and remains a concept for further study. Herein, taking the ternary OR and INHIBIT logic gates as model devices, we present the fabrication of a novel simple, fast, label-free, and nanoquencher-free system for multivalued DNA logic gates using poly-thymine (T) templated copper nanoparticles (CuNPs) as signal reporters. The mixture of Cu2+ and ascorbic acid (AA) is taken as a universal platform for all ternary logic gates. Different kinds of poly-T strands and delicately designed complementary poly-adenine (A) strands are alternatively applied as ternary inputs to exhibit the ternary output states (low/0, medium/1, high/2). Notably, there are no nanoquenchers in this platform as poly-A strands can function as not only inputs but also efficient inhibitors of poly-T templated CuNPs. Moreover, all DNA are unlabeled single-strand DNA that do not need sophisticated labeling procedures or sequence design. The above design greatly reduces the operating time, costs, and complexity. More importantly, the ternary logic computations can be completed within 20 min because of the fast formation of CuNPs, and all of them share the same threshold values.

Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2. The paper addresses the synthesis of balanced ternary reversible logic circuit and design of reversible half-adder and full-adder circuit by using balanced ternary reversible logic gates. We also introduce balanced ternary multiplier gate that is used to design of single trit and multi-trit multiplier circuit. Hardware complexity of each circuit is investigated.

Many-valued logics in general and 3-valued logic in particular is an old subject which had its beginning in the work of Łukasiewicz [Łuk]. Recently there is a revived interest in this topic, both for its own sake (see, for example, [Ho]), and also because of its potential applications in several areas of computer science, such as proving correctness of programs [Jo], knowledge bases [CP] and artificial intelligence [Tu]. There are, however, a huge number of 3-valued systems which logicians have studied throughout the years. The motivation behind them and their properties are not always clear, and their proof theory is frequently not well developed. This state of affairs makes both the use of 3-valued logics and doing fruitful research on them rather difficult.Our first goal in this work is, accordingly, to identify and characterize a class of 3-valued logics which might be called natural. For this we use the general framework for characterizing and investigating logics which we have developed in [Av1]. Not many 3-valued logics appear as natural within this framework, but it turns out that those that do include some of the best known ones. These include the 3-valued logics of Łukasiewicz, Kleene and Sobociński, the logic LPF used in the VDM project, the logic RM3 from the relevance family and the paraconsistent 3-valued logic of [dCA]. Our presentation provides justifications for the introduction of certain connectives in these logics which are often regarded as ad hoc. It also shows that they are all closely related to each other. It is shown, for example, that Łukasiewicz 3-valued logic and RM3 (the strongest logic in the family of relevance logics) are in a strong sense dual to each other, and that both are derivable by the same general construction from, respectively, Kleene 3-valued logic and the 3-valued paraconsistent logic.