Analysis of VLSI power supply network based on current estimation through magnetic field measurement

Abstract

The modern VLSI systems that demand high reliability require carefully-designed power/ground network to provide stable power supply. Though the power supply connection is verified before tapeout, it is quite difficult to evaluate its actual quality and reliability after fabrication. This paper proposes a novel way to evaluate the power supply network based on the measurement of magnetic field emission from LSI. The proposed method estimates the actual current flow from the magnetic field measurement results, and enables us to find defects or design faults such as VIA/wire disconnections and/or current concentration with low cost. Experimental result using an electromagnetic field simulator demonstrate that the proposed method precisely estimates the current flow in the supply network and clearly indicates the VIA fault location. To verify the feasibility of the proposed method with actual measurement results, the test structure is designed and fabricated in 0.18 μm 1P5M CMOS process.