Analysis of Single-Event Effects in Clock and Data Recovery Circuits Based on an LC Voltage-Controlled Oscillator

A clock and data recovery (CDR) circuit is one of the crucial blocks in high-speed serial link communication systems. The data received in these systems are asynchronous and noisy, requiring that a clock be extracted to allow synchronous operations. Furthermore, the data must be retimed so that the jitter accumulated during transmission is removed. This paper presents a novel architecture of CDR, which is very tolerant to long sequences of serial ones or zeros and also robust to occasional long absence of transitions. The design is based on the fact that a basic clock recovery having a clock recovery circuit (CRC) and a data decision circuit separately would generate a high jitter clock when the received non-return-to-zero (NRZ) data with long sequences of ones or zeros. To eliminate this drawback, the proposed architecture incorporates a data circuit decision circuit within the phase-locked loop (PLL) CRC. Other than this, a new phase detector (PD) is also proposed, which was easy to accomplish and robust at high speed. This PD is functional with a random input and automatically turns to disable during both the locked state and long absence of transitions. The voltage-controlled oscillator (VCO) is also designed delicately to suppress the jitter. Due to the high stability, the jitter is highly reduced when the loop is locked. The simulation results of such CDR working at 1.25Gb/s particularly for 1000BASE-X Gigabit Ethernet by using TSMC 0.25μm technology are presented to prove the feasibility of this architecture. One more CDR based on edge detection architecture is also built in the circuit for performance comparisons.

A new digital Voltage Controlled Oscillator (VCO) with the capability of fine tuning as well as coarse tuning controls is presented in this paper. Unlike conventional inverter-chain-based VCOs, the new design has more linear dependency of output frequency to input control voltage. The new VCO is a good candidate for modern Clock and Data Recovery (CDR) circuits because of this dual control. As a proof of concept, the functionality of the new VCO is verified in a CDR circuit used in a monolithic Serializer and Deserializer (SerDes) test chip fabricated in 0.5um ON Semiconductor process. The SerDes test chip was successfully tested at an operating frequency of 90MHz with a lock range of about 4.6 MHz due to the fine-tuning of the VCO. It is expected that using a more advanced process technology, a higher operating frequency can be easily achieved.

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.

A fully integrated clock and data recovery (CDR) circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-/spl mu/m CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and small K/sub VCO/ by employing the analog/digital dual loop architecture. It can relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem for wide data rate operations. All measured BERs are less than 10/sup -12/ with the data rate from 1.7Gbps to 3.125Gbps.

A 5-Gb/s clock and data recovery (CDR) circuit, incorporating 625 MHz interpolating voltage-controlled oscillators (VCO) and four-phase 1/8-rate phase detectors (PD), is demonstrated. The PD provides a linear characteristic that is proportional to the phase difference between the four-phase clocks and the input 5-Gb/s data, and hence produces four-demultiplexed 1.25-Gb/s outputs. The VCO is designed as a four-stage differential ring oscillator, employing the half-rate clock technique so that it can provide 1/8-rate clocks with delay interpolation. Test chips are fabricated in a 0.25 /spl mu/m CMOS technology. The whole chip occupies an area of 1.7/spl times/1.4 mm/sup 2/ together with on-chip low pass filters, i.e., two 16 pF capacitors and 63 k/spl Omega/ resistors. Post-layout simulations show that the recovered data output exhibits 40ps/sub p-p/ jitter characteristic for 2/sup 23/-1 PRBS serial NRZ input. The chip core dissipates 130 mW from a single 2.5 V supply.

An 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is reported. The integrated circuit (IC) is manufactured using an InP double heterostructure bipolar transistor (DHBT) technology which features cut-off frequency values of more than 220 GHz for both f/sub T/ and f/sub max/. The CDR circuit is mainly composed of a half-rate linear phase detector including an 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). The 40 Gbit/s recovered and demultiplexed data for an 80 Gbit/s input signal feature a signal swing of approximately 600 mV. The extracted 40 GHz clock signal shows a phase noise of -98 dBc/Hz at 100 KHz offset frequency. The corresponding peak-to-peak jitter amounts to 1.66ps while the rms jitter is 0.37ps. The full IC dissipates 1.65 W at a supply voltage of -4.8 V.

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.

A 2.5-Gb/s phase-lock clock and data recovery (CDR) circuit is proposed in system simulation for SONET OC-48 (2.488/2.666-Gb/s) transceiver applications. The CDR circuit exploits 1/4-rate linear phase detector. Making use of this technique the design of voltage controlled oscillator (VCO) facilitates and also it eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recover data.

This paper proposes a low-power referenceless clock and data recovery (CDR) circuit for biomedical devices or sensor applications. Its power consumption is reduced by adopting clock-edge modulation technique and using a voltage-controlled oscillator (VCO) based on a relaxation oscillator. Clock-edge modulation eliminates the need for an external reference clock without introducing the possibility of harmonic locking. Our CDR supports input data-rates between 200kbps and 10Mbps at 0.7V, and operate up to 24 MHz at 1.0V. The circuit is designed in a 0.18μm CMOS technology and consumes 8μW at an input data-rate of 10Mbps.

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.

An integrated clock and data recovery (CDR) circuit is a key element for optical communication systems at 40 Gbit/s. We present a fully integrated 40-Gbit CDR circuit fabricated using InP/InGaAs HBTs. The circuit contains a linear-type phase detector and a full-data-rate voltage-controlled oscillator. Error-free operation and wide eye opening were obtained for 40-Gbit/s pseudorandom bit sequence (PRBS) with a length of 2/sup 23/-1. The fabricated IC dissipates 1.71 W at a supply voltage of -4.5 V.

A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.

This paper proposes a low-power referenceless clock and data recovery (CDR) circuit for biomedical devices or sensor applications. Its power consumption is reduced by adopting clock-edge modulation technique and using a voltage-controlled oscillator (VCO) based on a relaxation oscillator. Clock-edge modulation eliminates the need for an external reference clock without introducing the possibility of harmonic locking. Our CDR supports input data-rates between 200kbps and 10Mbps at 0.7V, and operate up to 24 MHz at 1.0V. The circuit is designed in a 0.18μm CMOS technology and consumes 8μW at an input data-rate of 10Mbps.

본 논문에서는 다중점 위상검출기(Phase detector: PD)를 이용한 1Gbps 클럭 및 데이터 복원(Clock and data recovery: CDR)회로를 제안한다. 제안된 위상검출기는 데이터의 천이 모서리와 클럭의 상승/하강 모서리 3점을 비교하여 up/down 신호를 생성한다. 기존의 위상검출기 회로는 클럭 주기의 배수 만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기(Voltage controlled oscillator: VCO)를 조절하는 펄스폭변조(Pulse width modulation: PWM)방식을 사용한다. 제안된 위상검출기 회로는 클럭 반주기만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기를 조절하는 펄스수변조(Pulse number modulation: PNM)방식을 사용하여, 전압제어발진기를 미세하게 조절함으로써 지터를 줄일 수 있다. 제안된 위상검출기를 이용한 클럭 및 데이터 복원회로는 1Gbps의 전송률을 갖는 231-1개의 랜덤 데이터를 이용하여 테스트되었고, 지터와 전력소비는 각각 7.36ps와 12mW로 저전력, 적은 지터의 특징을 보였다. 제안된 회로는 0.18um CMOS 공정에서 1.8V 전원으로 설계되었다. The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps <TEX>$2^{31}-1$</TEX> pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented using a typical 0.18- $$\upmu $$ m CMOS process to justify the performance. The measurement results reveal that lock detector loop could reduce the voltage amplitude of Vctrl, which is the control of VCO. Notably, the voltage amplitude of Vctrl is reduced 75% from 1 V to 250 mV.