Abstract
AbstractMultiprocessor controlled electronic switching systems suffer from performance degradation due to common memory access contention. Therefore, there have been many studies on the common memory access contention. However, most of them deal with the case of equal access rate. This paper considers common memory access contention in multiprocessor controlled switching systems, in which one of the processors, called MCP, has a different common memory access rate than the other processors, called CPs. In this multiprocessor system, common memory access requests are served according to non‐preemptive priority discipline based on the processor type. This common memory access contention is modeled as a finite source queueing system with nonpreemptive priority discipline. The model is analyzed and the effect of nonpreemptive priority discipline on system performance (number of instruction steps executed) is evaluated, compared with the ordinary FIFO discipline.
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