Analysis and design of ion-implanted bubble memory devices

Abstract

4-μm period ion-implanted contiguous disk bubble memory circuits, designed and fabricated at AT&T Bell Laboratories, Murray Hill, NJ, have been investigated. Quasistatic testing has provided information about both the operational bias field ranges and the exact failure modes. A variety of major loop layouts were investigated and two turns found to severely limit bias field margins are discussed. The generation process, using a hairpin nucleator, was tested and several interesting failure modes were uncovered. Propagation on four different minor loop paths was observed and each was found to have characteristic failure modes. The transfer processes, both into and out of the minor loops, were investigated at higher frequencies to avoid local heating due to long transfer pulses at low frequencies. Again specific failure modes were identified. Overall bias margins for the chip were 9% at 50 Oe drive field and were limited by transfer-in.