An ultra-low-power CMOS voltage-controlled ring oscillator for passive RFID tags

Abstract

An ultra-low-power CMOS voltage-controlled ring oscillator (VCRO) for passive ultra-high-frequency (UHF) radio-frequency identification (RFID) tags is presented. The gates of the complementary CMOS transistors in pseudo-differential (PD) delay cells are biased through quasi-floating gate (QFG) technique. The boosted gate-drive voltage enables operation of the differential delay cells with supply voltages smaller than the minimum required overdrive voltage of the two stacked transistors and accordingly facilitates the oscillation at ultra-Iow-power regime. QFG biasing technique also offers an additional control knob to tune the output frequency of the ring oscillator. The proposed two-stage PD-VCRO is designed and laid-out in a standard 0.13-μm CMOS technology. A voltage level converter is also presented to interface the output of the proposed VCRO with the succeeding circuitry. The entire VCRO core occupies an area of 25 μm×20 μm For a supply voltage of as low as 140 mV, an output frequency of 4 MHz is achieved at 3.6 nW power consumption. Although the intended application for the proposed VCRO is passive RFID tags, the architecture can be used in other ultra-low-power applications.