An optimized design for Fused add-multiply operation

Abstract

Many digital Signal processing (DSP) applications requires complex arithmetic operation which is carried by multiplier and adder units. Multiplication operation can be done as a successive addition which introduces delay in the processing. In which implementation of this technique with delay constraints leads to more challenging. Because the internal modules generate delay in propagation of processed output of adder unit. With a solution to this problem, the optimized method of multiplier and adder units are fused in a single module with modified booth encoding called Fused add multiply (FAM) is designed. It reduces the delay of the summing operation and produce a direct recoded value of the sum A+B (F=A+B), called SUM to MODIFIED BOOTH RECODER (S-MB). The recoding operation is explored by incorporating them in FAM design. With these recoded bits, the multiplicand generates minimum number of partial products in which it reduces the time Complexity for addition operation. The Products are feed to carry save adder and to Carry look ahead adder to obtain the final resulted output. By these techniques the design yields optimized reduction in critical delay, hardware complexity and power consumption Compared to the existing multiplier design.