An optimised SDD ATPG and SDQL computation method across different pattern sets

Abstract

Small delay defect (SDD) ATPG has been around for a few years now; however, its adoption is not prevalent due to various reasons. (i) Unique detection with SDD ATPG patterns over transition delay fault (TDF) ATPG patterns is often not easy to establish due to the large volume of the former and the insistence on coverage due to the latter. (ii) Lack of a seamless method to target SDD patterns for nodes which are embedded in paths with small slack and TDF patterns for the other nodes further inhibits SDD ATPG. In this paper, we present methods to address both these limitations. We describe a method for targeted SDD pattern generation for SDQL (statistical delay quality level) improvement across logic modules in multiple clock domains (at different frequencies) based on slack intervals. We also describe a method to incorporate patterns corresponding to other fault models suitably (namely TDF and PDF - path delay fault) to improve the SDQL metric without significant pattern volume inflation. Results on a large SOC indicate a reduction in the test pattern volume ranging from 45% to 92%, and an SDQL improvement ranging from 48% to 85%, as compared to standard methods in use today.