Abstract
The potential for use of porous silicon in designing varicaps with high capacitance ratios satisfying the requirements of microelectronics and microsystems engineering is considered. The technique for the fabrication of capacitor structures via the electrodeposition of copper onto porous silicon is presented. The morphological features of the obtained structures are examined and the specific capacitance of varicaps is determined. The prospects for the application of varicaps based on porous silicon in integrated electronics are outlined.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
