An input signal dependent 8-to-12 bit variable resolution SAR ADC with digitally implemented bit enhancement Logic

Abstract

This paper presents variable resolution SAR ADC with digitally implemented Bit enhancement logic. Unlike conventional approaches, this work avoids complex hardware architecture to reduce power consumption as the variable resolution is achieved using digitally implemented VRL (Variable Resolution Logic) block instead of combining different ADC configurations altogether. The proposed architecture utilizes the VRL block to enhance the resolution. This work first uses the linear range of an 8-bit SAR ADC as a learning dataset and then uses corresponding output bits as training data for VRL block. This VRL block further enhances the resolution with the help of a 2-bit voltage-to-digital converter by self-adjusting the required resolution after estimating the error. Less variation in sampling rate from 250 MHz to 175 MHz is achieved after implementing the VRL block. The proposed architecture is designed in 180 nm CMOS technology to validate the work. The simulation results show the ADC achieves an SNDR of 47.4 dB for 8-bit and increases to 72.11 dB for 12-bit resolution. The FoM of 253 fJ/conversion step for 8-bit SAR ADC is achieved, and it ranges from 168.3 to 35.7 fJ/conversion step in Variable resolution block phase. The area of the proposed ADC is 315.86 × 151.30 µm2.