Abstract
Linear placement has several applications in the design of very large scale integrated (VLSI) circuits. Several authors have recently shown that node clustering or compaction enhances the performance of iterative algorithms. This paper describes a technique to extract clusters by means of an algorithm that identifies a maximum weight matching in a path graph in linear time. The resulting linear placement algorithm (CLP) combines node compactions and iterative improvement in an efficient and effective approach. The benefit of compaction is quite visible. Comparisons of the results of CLP with and without compaction on several test cases show the dramatic effect of compaction on the final solution. The approach of CLP is an efficient improvement of the linear placement algorithm of Saab and Chen [1994]. On many instances with known optimal solutions, CLP also achieves an optimal solution. The dependency of the results of CLP on the initial placement is minimal, since solutions found by CLP using many different starts do not significantly differ from each other. Under suitable assumption, CLP can be shown to run in O(nP), where n and P are the number of nodes and the number of pins of the input circuit, respectively.
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