An FPGA-Based, 12-Channel TDC And Digital Signal Processing Module For The RatCAP Scanner

Abstract

Front end digital signal processing and VME based DAQ electronics for the RatCAP (Rat Conscious Animal PET) is discussed. All digital approach to front end signal processing for the mobile animal PET scanner is presented. Altera Cyclone family FPGA based realization of the 12 channel TDC (time to digital converter), address serial decoder and VME based DAQ system development is discussed in detail. Routing delays between logic array blocks combined with propagation delay of logic cells were used to generate different clock phases, to achieve subclock speed resolution. Altera LogicLock/spl trade/ toolsets were used for replicable and tighter placements of the supporting logic to achieve the required timing performance. TDC realized using controlled placements of the logic elements to specific logic cells within a specific LAB (logic array block) has the maximum DNL of 0.7 ns. VME based custom designed board with FIFO memory constituted the DAQ electronics. Test results with full 12 blocks, RatCAP front end electronics are presented. TDC realization and characterization is discussed in details. Timing spectrum obtained for 12 blocks, 384 channels of full RatCAP scanner is also presented.