An FPGA SAT solver based on enhanced constraint

Abstract

As the first NP-complete problem, the Boolean satisfiability (SAT) problem is the key problem in computer theory and application. FPGA has been address frequently to accelerate the SAT solving process in the last few years, owing to its parallelism and flexibility. In this paper, we have proposed a novel SAT solver adopting an improved local search algorithm on the reconfigurable hardware platform. The new software preprocessing procedure and hardware architecture are involving to solve large-scale SAT problem instances. As compared with the past solver, the solver has the following advantages:(1) the preprocessing technology can strongly improve the efficiency of solver; (2) the strategy of strengthening the variable selection can avoid the same variable flipped continuously and repeatedly. It reduces the possibility of searching into local optimum. The experiments have shown that our solver has better performance than previous works.