Abstract
Energy efficiency remains one of the main factors for improving the key performance markers of RRAMs to support IoT edge devices. This paper proposes a simple and feasible low power design scheme which can be used as a powerful tool for energy reduction in RRAM circuits. The design scheme is exclusively based on current control during write and read operations and ensures that write operations are completed without wasted energy. Self-adaptive write termination circuits are proposed to control the RRAM current during FORMING, RESET and SET operations. The termination circuits sense the programming current and stop the write pulse as soon as a preferred programming current is reached. Simulation results demonstrate that an appropriate choice of the programming currents can help obtain 4.1X improvement in FORMING, 9.1X improvement in SET and 1.12X improvement in RESET energy. Also, the possibility to have a tight control over the RESET resistance is demonstrated. READ energy optimization is also covered by leveraging on a differential sense amplifier offering a programmable current reference. Finally, an optimal trade-off between energy consumption during SET/RESET operations and an acceptable read margin is established according to the final application requirements.
Highlights
Memory is an essential component of today’s electronic systems
Monte Carlo (MC) simulations are performed for specific IrefR and IrefS currents picked from Fig. 18 in order to track the evolution of the read margin versus variability
A new energy saving design approach based on a strict control of Resistive RAM (RRAM) programming and reading currents is introduced
Summary
Memory is an essential component of today’s electronic systems. It is used in any equipment using a processor such as computers, smart phones, tablets, digital cameras, entertainment devices, global positioning systems, automotive systems, etc. As the voltage across the memory cell VR is maintained after the switching event, the current IR keeps flowing through the cell These fast cells can be over-RST or overSET resulting in an uncontrolled spread of High Resistance State (HRS) and Low Resistance State (LRS) distributions. The READ current can be relatively large for over-SET cells (tens of μA) as these cells end in a very low LRS resistance The latter can limit performances of read-intensive applications generally associated with inmemory processing and with Neural Network (NN) applications where synaptic weights are constantly and simultaneously read during inference [14]. To the authors’ knowledge, this is the first work presenting a full low-power design-scheme targeting all operating modes of RRAM memory circuits.
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