An Efficient Parallel Computing Framework for Over the Obstacle VLSI Routing

Abstract

Constructing a fast and efficient rectilinear Steiner minimal tree (RSMT) in the presence of obstacle/blockage is a major issue in VLSI physical design (PD). The existing method considers maze routing method for addressing obstacle-avoiding RSMT (OARSMT) problem. However, using OARSMT can induce longer wire length (WL) and routing delay. Further, in existing model, only slew constraint is considered and delay constraint are neglected. This results in wastage of routing resources (i.e. due to higher buffer size). For overcoming these problems, this work presents an efficient routing over obstacle-based RSMT construction that satisfies delay requirement. Further, we present an efficient parallel computing architecture to enhance RSMT construction (i.e. in parallel manner) under multicore environment (i.e. CPU and GPU). Experiments are conducted on small to large nets with blockages. The outcome achieved in the proposed routing method is to reduce wire length and attain better speedup when compared with sequential and existing VLSI routing model.