An efficient algorithm for dual-voltage design without need for level conversion

Abstract

We propose a technique to use dual supply voltages in digital designs to reduce energy consumption. New algorithms are proposed for finding and assigning a lower voltage in a dual voltage design. Given a circuit and a supply voltage and an upper bound on the critical path delay, the first algorithm finds an optimal lower supply voltage and a second algorithm assigns that lower voltage to selected gates. A linear time algorithm described in the literature is used for computing slacks for all gates of the circuit for a given supply voltage. For the computed gate slacks and the lower supply voltage, all gates are divided into three groups such that no gate in the first group can be assigned the lower supply, all gates in the second group can be simultaneously set to lower supply while maintaining positive slack for every gate, and gates in the third group are assigned low voltage, iteratively, in selected subsets at a time. The gate slacks are recalculated after each such voltage assignment. Thus, the overall complexity of this reduced power dual voltage assignment procedure is O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). SPICE simulations of ISCAS'85 benchmark circuits using the 90-nm bulk CMOS technology results show up to 60% energy savings.