Abstract
Many image filtering techniques can be accelerated with compute unified device architecture (CUDA)-based massively parallel implementations. In this paper, we show the major issues on our acceleration techniques, and also its implementation details. We implemented various image filtering operations in our own CUDA kernel programs, and they are combined to build an artifact-detection scheme in PCB board soldering process. We designed our own computational logics on the artifact detection, and finally, the whole system figure out the potential artifact regions. Comparing with the central processing unit-based reference implementation, we show its correctness and feasibility, with much execution speed-ups.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
