An area-delay efficient single-precision floating-point multiplier for VLSI systems

Abstract

The floating-point multiplier (FPM) is the most commonly used component in various image and signal processing applications. An area-delay efficient FPM design could be helpful for the development of high-performance VLSI computing systems. Therefore, this paper presents the analysis of single-precision FPM to find the possibilities for the reduction in delay and area. From the analysis, it is found that the delay of FPM depends on the delay of mantissa multiplication and exponent normalization units. Based on the above observations, in this paper, the delay and area efficient mantissa multiplication and exponent addition-cum-normalization units are proposed. Further, using these components, the single-precision FPM structure is proposed. Synthesis results show that the proposed FPM design offers a saving of 15.3% in delay and 10.8% in area compared to the best available existing FPM design. Besides, the proposed FPM consumes 13.0% less power-delay-product and involves 24.4% less area-delay-product in comparison to the best available existing design. Finally, effectiveness of the proposed single precision floating-point multiplier is presented in Gaussian smoothing filter of the image processing application.