An Area Optimized Barrel Shifter Design

The critical challenge in designing complex digital circuits automatically using an evolutionary algorithm is to overcome the scalability issue caused by combinatorial explosion. Because of this problem, the existing evolutionary design methods can deal with digital circuits composed of only a small number of bits. To resolve this problem, a novel evolutionary design method is proposed on the basis of hierarchical module structures and predominant component prevention. From extensive experiments, it is found that this method can automatically design digital circuits composed of a large number of bits within a polynomial time.

Most digital circuits which have been developed to implement algorithms, can benefit from an increase in clock speed, but do not completely map the problem to all available silicon resources. We have introduced a hardware based scheme capable of effectively using technology, specifically the increase in silicon area, to improve the computational time of complicated applications. In this thesis, we applied this scheme to solve the factoring problem, which requires exponential time (with respect to the number of bits in n) in conventional computers and could be only solved in polynomial time with quantum computers. The scheme successfully mapped the problem to most of the silicon area of Altera Stratix FPGA. The results show that the scheme is capable of reducing the time complexity to a polynomial rate with respect to the number of bits of the number n. The results also show an exponential rate of use for silicon with respect to the number of bits of n. Our analysis shows that the new scheme is scalable with technology speed and available space, could be applied to other applications to solve the performance limitations of conventional systems.

Most digital circuits which have been developed to implement algorithms, can benefit from an increase in clock speed, but do not completely map the problem to all available silicon resources. We have introduced a hardware based scheme capable of effectively using technology, specifically the increase in silicon area, to improve the computational time of complicated applications. In this thesis, we applied this scheme to solve the factoring problem, which requires exponential time (with respect to the number of bits in n) in conventional computers and could be only solved in polynomial time with quantum computers. The scheme successfully mapped the problem to most of the silicon area of Altera Stratix FPGA. The results show that the scheme is capable of reducing the time complexity to a polynomial rate with respect to the number of bits of the number n. The results also show an exponential rate of use for silicon with respect to the number of bits of n. Our analysis shows that the new scheme is scalable with technology speed and available space, could be applied to other applications to solve the performance limitations of conventional systems.

Growing demand for high-speed Ising-computing-specific hardware has prompted a need for determining how the accuracy depends on a hardware implementation with physically limited resources. For instance, in digital hardware such as field-programmable gate arrays, as the number of bits representing the coupling strength is reduced, the density of integrated Ising spins and the speed of computing can be increased while the calculation accuracy becomes lower. To optimize the accuracy-efficiency trade-off, we have to estimate the change in performance of the Ising computing machine depending on the number of bits representing the coupling strength. In this study, we tackle this issue by focusing on the Hopfield model with discrete coupling. The Hopfield model is a canonical Ising computing model. Previous studies have analyzed the effect of a few nonlinear functions (e.g. sign) for mapping the coupling strength on the Hopfield model with statistical mechanics methods, but not the effect of discretization of the coupling strength in detail. Here, we derived the order parameter equations of the Hopfield model with discrete coupling by using the replica method and clarified the relationship between the number of bits representing the coupling strength and the critical memory capacity. In this paper, we used the replica method for the Hopfield model with general nonlinear coupling (Sompolinsky (1986)) to analyze the model with a multi-bit discrete coupling strength, and we novelly derived the de Almeida-Thouless line of the model with general nonlinear coupling.

Adiabatic switching techniques based on energy recovery principle are one of the best solutions at circuit and logic level to achieve reduction in power. The main objective of this paper is Low Power Multiplexer design using diode free adiabatic logic and implementation of this logic into barrel shifter. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits. It can be implemented as a sequence of multiplexers (mux), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance. The number of multiplexer required is N log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N. This paper compares conventional CMOS based design with diode free adiabatic logic (DFAL), the simulation is performed using a SPICE circuit simulator at 0.18um technology node & 1.8V standard CMOS process. Comparison has shown a significant power saving to the extent of 60% in case of diode free adiabatic technique as compared to CMOS logic in 10-100MHz transition frequency range.

Signal processing is frequently discussed topic nowadays. Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) can process data at high rates. Arithmetic operations such as addition, subtraction, multiplication, division or square root are often used in DSP and FPGA. Several algorithms for square root computation on FPGA were designed in past years. This paper describes a proposal of single clock square root algorithm applicable on FPGA. The algorithm is formulated generally for any number of bits. Simulations and experiments for 16-bits binary numbers have confirmed that obtained results are equal to square root values rounded to nearest integer.

Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. Their conversion consists of two stages: Sampling, which maps a continuous-time signal into discrete-time, and quantization, i.e., representing the continuous-amplitude quantities using a finite number of bits. ADCs typically implement generic uniform conversion mappings that are ignorant of the task for which the signal is acquired, and can be costly when operating in high rates and fine resolutions. In this work we design task-oriented ADCs which learn from data how to map an analog signal into a digital representation such that the system task can be efficiently carried out. We propose a model for sampling and quantization that facilitates the learning of non-uniform mappings from data. Based on this learnable ADC mapping, we present a mechanism for optimizing a hybrid acquisition system comprised of analog combining, tunable ADCs with fixed rates, and digital processing, by jointly learning its components end-to-end. Then, we show how one can exploit the representation of hybrid acquisition systems as deep networks to optimize the sampling and quantization rates given the task by utilizing Bayesian meta-learning techniques. We evaluate the proposed deep task-based ADC in two case studies: the first considers synthetic multi-variate symbol detection, where multiple analog signals are simultaneously acquired in order to recover a set of discrete symbols. The second application is beamforming of analog channel data acquired in ultrasound imaging. Our numerical results demonstrate that the proposed approach achieves performance which is comparable to operating with high sampling rates and fine resolution quantization, while operating with reduced overall bit rate. For instance, we demonstrate that deep task-based ADCs enable accurate reconstruction of ultrasound images while using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$12.5\%$</tex-math></inline-formula> of the overall number of bits used by conventional ADCs.

Timing-critical path analysis is one of the most significant terms for the VLSI designer. For the formal verification of any kinds of digital chip, static timing analysis (STA) plays a vital role to check the potentiality and viability of the design procedures. This indicates the timing status between setup and holding times required with respect to the active edge of the clock. STA can also be used to identify time sensitive paths, simulate path delays, and assess Register transfer level (RTL) dependability. Four types of Static Random Access Memory (SRAM) controllers in this paper are used to handle with the complexities of digital circuit timing analysis at the logic level. Different STA parameters such as slack, clock skew, data latency, and multiple clock frequencies are investigated here in their node-to-node path analysis for diverse SRAM controllers. Using phase lock loop (ALTPLL), single clock and dual clock are used to get the response of these controllers. For four SRAM controllers, the timing analysis shows that no data violation exists for single and dual clock with 50 MHz and 100 MHz frequencies. Result also shows that the slack for 100MHz is greater than that of 50MHz. Moreover, the clock skew value in our proposed design is lower than in the other three controllers because number of paths, number of states are reduced, and the slack value is higher than in 1st and 2nd controllers. In timing path analysis, slack time determines that the design is working at the desired frequency. Although 100MHz is faster than 50MHz, our proposed SRAM controller meets the timing requirements for 100MHz including the reduction of node to node data delay. Due to this reason, the proposed controller performs well compared to others in terms slack and clock skew.

This paper focused on the design of a 2+1- order Switched-current MASH Delta-Sigma ADC with the digital cancellation circuit in TSMC 0.18-µm 1P6M CMOS process. To combat errors in MASH architectures, we have to cancel the errors by utilizing a pertinent digital cancellation circuit; the output of digital code contains the numbers and position of characteristics to the latter part of the digital filter to facilitate the processing. We proposed an algorithm for the logic circuit and employed simplified delay block in digital cancellation circuit to cancel the noise errors from the earlier stage, and to generate a third-order noise shaping output. Our simulation results show that signal-to-noise and distortion ratio (SNDR) is 90.4 dB, and the effective number of bits (ENOB) is 14.73 bits at a sampling rate of 10.24 MHz with an oversampling ratio (OSR) of 256, and the signal bandwidth is 20 kHz. This design draws 12.99 mWfrom the supply voltage of 1.8V and occupies a core area of 0.14 mm2.

The decrease of surface area is a critical concern for any type of digital circuit. For example, the VLSI approach is used to lower the chip's size, which increases both the device's density and its performance. When it comes to digital circuits, a full adder circuit is a crucial part of any arithmetic processor. A computer, or any other type of computer, will have this component. Most arithmetic operations performed as of now are 64 bits. As a result, we need a sizable amount of room to complete this procedure. We can also take use of these advantages even if we increase the number of bits that need to be processed in parallel. This research attempts to demonstrate how a 4-bit CMOS-based full adder circuit is designed and simulated using Microwind and DSCH at various technology levels. It is then compared to determine if the transistor size may help achieve those benefits. Afterwards. A four-bit binary addition is the goal of the circuit that was built. A 4-bit full adder may be built using a totally automated CMOS design process. The concept and layout of a 4-bit full adder are developed in the initial CMOS design. With nodes of 90, 65 and 45 nm, the designs are produced and modelled utilizing technology. Digital integrated circuits with smaller nodes perform better when compared to those with larger ones, according to simulation findings and distinct outputs.

As soft-hardware-logic circuits had been proposed in the literature as an alternative for digital circuits taking advantage the fact that any Boolean function could be implemented with the same cell, just configuring external signals, this work shows a methodology that could be followed particularly for the design of a four bits logic gate, using the so-called neuron MOS transistor (ν-MOS). Simulation results show the feasibility of the design for performing as XNOR, NOR, OR, XOR, AND or NAND logic gates, for instance. In order to extrapolate the design to a higher number of bits, the key issue is to properly consider the weight of the input capacitances in correlation with the number of input bits. A D/A converter can be used as the input stage of the configuration. This design considers the D/A converter-less version, since it helps to increase device integration as the number of transistors used is reduced with no difference in its performance. The design should be based on the theoretical floating potential diagram (FPD) of the desired logic gate.

A novel technique is described for realizing a high-performance digital circuit using neural networks. As examples of applications of neural networks to digital circuits, an adder and a multiplier using neural networks are proposed. High-speed digital circuits can be realized because the neural networks have almost constant operation time regardless of the number of bits in the circuit. The principle of the adder and multiplier is described in detail, and some simulation results obtained with these circuits are presented. >

Chapter four covers problems concerning the realization of digital control algorithms. The following realizations of digital control circuit are considered: digital signal processors, microprocessors, microcontrollers, and programmable digital circuits. All these solutions are compared. The general problems of analog signal acquisition for digital control circuit, such as sampling rate, number of bits, signal to noise ratio (SNR), anti-aliasing filter, bandwidth of signal, signal range are discussed too. Digital filter and filter bank are also considered, with special emphasis filters which are useful for active power filter (APF) control circuit, sliding discrete Fourier transform (DFT). Special attention is paid to improve APF dynamic range and using a non-causal solution it is possible to dump output stage dynamic distortion. For unpredictable loads a three-phase multirate APF with modified output inverter was designed. Finally, experimental test result of considered APF is presented and discussed.KeywordsDiscrete Fourier TransformFilter BankDigital Signal ProcessorTotal Harmonic DistortionActive Power FilterThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Sigmoid functions are used as transfer functions in artificial Neural Networks (NN). Normally, NNs are implemented in processors systems, both in training and testing phases. But in some scenarios these systems do not reach real time operation. In these cases, the NNs can be implemented in specific digital devices. For prototypes design it is convenient to use Field Programmable Gate Arrays (FPGA). The sigmoid functions are non-linear systems; therefore, they are not directly implementable in fixed point format, and some approximations are used. A very used one is the lookup table technique. In this paper, an advanced design method based on Matlab and Simulink is presented. It allows scan the number of samples and the number of fractional bits in input and output. The Signal to Noise Relation power (SNR) is used to measure the approximation functionality. This allows to observe linearities in physical performances against the number of bits address bus or the number of words in the lookup table. The automatic generation code to a Hardware Description Language (HDL) is possible. The HDLs can be Very High Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog.

Correlation techniques are widely used in analog and digital signal processing; e.g. in optiman receiver design. In this paper, a new digital output correlator circuit design is proposed. The correlation results are presented as a binary count of the number of bits in agreement between 31-bit reference and input sequences. Correlation results could be presented at data rates up to about 50MHz. The proposed new circuit could be implemented in a high speed bipolar transistor technology as a monolithic large-scale-integrated circuit with a power dissipation of about .5 watts. A novel pipelined 31-bit digital summing circuit will be presented that employs new multivalued, multithresholded latching and counting circuits in the formation of its binary-coded output. Comparisons with an all-binary digital correlator circuit are made.