An Architecture With Pipelined Background Suppression and In-Situ Noise Cancelling for 2D/3D CMOS Image Sensor

Abstract

We present a CMOS image sensor with integrated background suppression scheme for detecting small signals out of unwanted background signals. For the background suppression, differential signals with suppressed common-mode background signals are sampled within a short sub-sensing time in order to avoid the saturation from strong background signals. Analog differential signals are digitally accumulated multiple times in one integration time for high SNR. The column-parallel background suppression circuits are pipelined in order to achieve short sub-sensing time. Moreover, additional operations for the noise cancelling are merged with the background suppression and no extra timing for the noise cancelling is required during the sub-sensing time. In order to suppress stronger background signals, sensitivity can be adjusted to be decreased using in-pixel capacitors when strong background signals are present. The prototype image sensor with 1328 $\times$ 1008 pixel array has been fabricated with a 0.11 $\mu{\rm m}$ 1P4M CIS process. We have successfully captured images from the fabricated sensor chip with strong background signal over 10 klx scene illuminance without optical filters. The background-to-signal ratio is 32.1 dB.